DVClub Silicon Valley Online – May 15, 2020 – Guest Speakers: Dave Rich (Mentor) & Michael Bode (Arm)

DVClub Silicon Valley online!

Please join us on May 15, 2020 for DVClub Silicon Valley Online!  Dave Rich, a member of the Flows and Methodology Product Engineering team at Mentor, and Michael Bode, a Design Engineer at Arm will be presenting. 

• 12:00pm PDT — Presentations by Dave Rich & Michael Bode


• All registrants will receive a link to the online event as we get closer to May 15th.

On behalf of DVClub, we hope you are all staying healthy in these “socially distant” and difficult times, and we look forward to seeing you on May 15th! 

Presentation #1

 “SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results” by Dave Rich (Mentor, a Siemens Business)

Constrained Random Verification (CRV) addresses the time-consuming task of writing individual directed tests for complex systems. We sometimes say that CRV automates writing tests for quickly producing the test cases you can think of, or hitting the corner cases you didn’t. But the reality is, like with any computer programming language, your code executes exactly the way it is written, and has no concern for what you were thinking. In particular when coding constraints, this manifests as results that satisfy the constraints, but may not match what you intend. Crashes or conflicting constraint failures are usually easier to resolve because of their abrupt termination. However, without an abrupt termination, you may not notice anything wrong with the results until much later in the process; perhaps after you check your functional coverage reports. This talk explores two of the most common issues when constraint solver results do not match your intent: 1) not understanding how Verilog expression evaluation rules apply to interpret the rules of basic algebra, and 2) not understanding the affect probability has on choosing solution values. These are subjects you may have learned (or slept through) in school long ago and need refreshing. This talk presents a background defining how SystemVerilog constraints work, and how these issues play into getting unwanted results. Also, it offers a few coding recommendations for improving your code to get better results along the way.

• Dave Rich is member of the Flows and Methodology Product Engineering team.  He is chartered with streamlining our testbench flows as they interact with a number of Mentor’s products, especially around the Questa Simulation platform. Dave brings over three decades of design and verification experience to bear on developing advanced verification methodologies. He has been actively involved in the standardization of SystemVerilog, via Accellera and then the IEEE, where he has served as co- chair of the Technical Champions committee in the SystemVerilog IEEE 1800 Working Group. At Mentor Graphics, Dave was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM). Recently, Dave was working for the Mentor Consulting Division where he was driving the adoption of our simulation technologies with various customers. Prior to that, Dave worked on early simulation and synthesis technologies at Cadence and Synopsys.

Presentation #2

 “How Design Verification Fits into a Functionally Safe World” by Michael Bode – Arm

The automotive market and other industries requiring functional safety have had an increasing demand for performance bandwidth, which has led to enabling increasingly complex CPU and SoC for use.  A key function of these standards are elevated integrity levels, which makes design verification an essential gate-keeper for the quality metrics of the IP. 

• Michael Bode has been a design engineer for the past 20 years in the consumer SoC space. He has spent the last nine years at Arm on the application processor IP team with the last five as a safety engineer dedicated to ensuring those application processors meet the necessary standards to support functional safety applications.  

RSVP and invite some of your colleagues!