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DVClub Silicon Valley – October 11 – Presenter: Greg Smith (Oracle) – Tutorial: Andy Stein (Avery Design Systems)


October 11, 2017


11:30 am - 02:30 pm

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Dave and Buster's

940 Great Mall Dr., Milpitas, CA 95035

Milpitas, CA, US, 95035

Please join us on October 11th at Dave and Buster’s for a catered lunch and networking. Greg Smith of Oracle Corporation will be our speaker, and Andy Stein of Avery Design Systems will present the tutorial.

  • 11:30am—Door Open / Networking

  • 12:00pm—Lunch / Presentation by Greg Smith of Oracle

  • 12:50pm—Tutorial by Andy Stein of Avery Design Systems


“Functional Coverage is Useless” by Greg Smith, Oracle Corporation

Greg’s talk will observe the evolution in the use of coverage to measure verification completeness and tape out readiness.  His talk suggests that we are at an inflection point in the evolution of coverage where current methods are grossly inadequate.  He will suggest some directions in which coverage may evolve to meet the demands of today’s complex SoCs..

  • Greg Smith has been a verification engineer for all of his 30 year career.  Processor verification has been the primary focus for nearly all of that time.  Greg is a Director of Processor verification at Oracle/Sun where he has worked for the past 10+ years.  Before that Greg worked at HP and Multiflow.  Greg’s role at Oracle, besides managing the verification of next generation SPARC cores, is as a driver of innovation to devise new techniques to improve tape out quality and improve engineering efficiency.  Greg is a passionate proponent of the use of metrics to measure verification efficiency and quality.


Improving ‘Gate Simulation Signoff’ throughput by handling the noise from False X’s by Andy Stein, Avery Design Systems 

Many companies that are using gate simulation to verify functionality already understand that despite efforts to clean up potential “X” issues in RTL, their post-synthesis and optimization results can produce additional sources of “X” in their gate netlist. Some of the effects of the “X’s” in gate simulation are not real, but are mainly artifacts of Verilog simulation being overly pessimistic.  As design and verification engineers race against the clock to analyze the results to find real problems, the noise created by the false X’s can cause too much time wasted. As such, some companies have more brute force methods, such as initializing all flops to some arbitrary value and run multiple simulations to hope they have not masked a real issue.  Avery Design Systems has had a product on the market for many years , SimXACT, to help companies take a more conservative approach to removing the noise from false X’s, by applying the tool dynamically during simulation to remove those false X’s  and using formal analysis to prove the correctness of the fixes.


RSVP NOW! Feel free to invite some of your colleagues as well.

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