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DVClub Silicon Valley – July 11, 2018 – Presenters: Dave Burgoon (Microsoft) & Josh Rensch (GlobalFoundries)

Details
Date:

July 11, 2018

Time:

11:30 am - 02:30 pm

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Organizer

DVClub

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Venue

Dave and Buster's

940 Great Mall Dr., Milpitas, CA 95035

Milpitas, CA, US, 95035

Please join us on July 11, 2018 at Dave and Buster’s for a catered lunch and networking.  Dave Burgoon, a Senior Design Verification Engineer at Microsoft will give a presentation on functional verification of High-Level-Synthesis models, and Josh Rensch of GlobalFoundries will give a presentation on team building.



  • 11:30am — Doors Open / Networking

  • 12:00pm — Lunch / Presentations by Dave Burgoon (Microsoft) & Josh Rensch (GlobalFoundries)

  • 1:00pm   — Networking


 


 Presentation #1


“UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs” by Dave Burgoon, Microsoft


HLS (High-Level Synthesis) tools allow us to raise the level of abstraction of our hardware design models from RTL (Register Transfer Level) written in Verilog to a much higher, untimed level written in C++.  These tools produce Verilog RTL models that are fed to conventional RTL-to-gates synthesis tools, the output of which flow into the physical design process.  The advantages of working at this higher level of abstraction are well-documented.  These include engineering productivity (e.g. fewer design coding errors), faster time to market, and the ability to quickly modify or leverage a design.


How are we to directly verify the source HLS model?  Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog.  This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.



  • Dave Burgoon has B.S. in Electrical Engineering, summa cum laude, from the University of Toledo, and an M.S. in Computer Science from Colorado State University.  He has two U.S. patents, and has made various contributions over the years to industry conferences and publications, including DVCon, its predecessors (IVC/VIUF and HDLCon), DesignCon, and the Design Automation Conference. Dave is a Senior Member of the IEEE, and has over 36 years of experience in hardware design, verification, and functional modeling.  He is presently a Senior Design Verification Engineer on Microsoft’s Custom Silicon Development team, which develops SoCs, chipsets, and sensors for Xbox, HoloLens, and other devices.


 


Presentation #2


“Team Building is as Easy as Stealing a Car” by Josh Rensch, SoC Verification Lead, GlobalFoundries


Teams accomplished most of the great things in this world. Teams of engineers created wonders – from the Titan Rockets to the Xbox and from the MRI to the iPhone. Those teams needed to work cohesively.  Building a well-oiled team shouldn’t have the same level of tension as a Hollywood action movie. There is an underlying trait that all great teams have.  Josh will share this secret, and some adventures, from over ten years of team building in the verification space, all to help you build better teams and achieve first pass success.



  • Josh Rensch is an SoC Verification Lead at GlobalFoundries in Rochester, MN. In his career he’s worked on the F-35 and the PlayStation 3. Since 2004, he’s been leading teams for big companies, small companies and a few in-between. He has a couple patents and several missed family dinners to show for it. In his spare time, he makes custom bacon, plays board games and works with special needs parents.


 


RSVP NOW and invite some of your colleagues as well!

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