DVClub Fort Collins – April 27, 2018 – Presenters: Amol Bhinge (NXP), Alan Pippin (HPE) & Dave Burgoon (Microsoft)
Please join us on April 27, 2018 at the Fort Collins Marriott for a catered lunch and networking. We are excited to announce that we will have three speakers for this event: Amol Bhinge, Design Verification and Emulation Director at NXP, Alan Pippin, an Expert Technical Lead at Hewlett Packard Enterprise, and Dave Burgoon, a Senior Design Verification Engineer at Microsoft will be our guest speakers!
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch & Presentations by Amol Bhinge of NXP, Alan Pippin of HPE, and Dave Burgoon of Microsoft
- 1:30pm — Networking
“SoC Design Verification: Challenges, Innovations and Beyond” by Amol Bhinge, NXP
SoC Verification continues to expand scope with ever demanding multi-variable equations for schedule, resources, quality, and complexity. This presentation attempts to cover several aspects of SoC verification, from the basics to advanced technologies.
- Amol Bhinge is working as Global Design Verification and Emulation Director at NXP Semiconductors in Austin, TX. Amol has been at NXP Freescale Semiconductor/Motorola for the past 14+ years. He has an MS degree in Electrical Engineering from the University of Minnesota. He has 8 US Patents, all related to verification tools and methodologies. Amol continues to be the focal point for bringing in new verification technologies, driving collaboration/communications with EDA vendors, prioritizing issues related to vendors, and representing his organization on verification related topics. He has also served as a member of the Accellera UCIS-TSC that standardized and rolled out UCIS 1.0. Amol is a regular contributor to EDA User Group and Verification Conferences.
“Big Data in Verification: Making Your Engineers Smarter” by Alan Pippin, Hewlett Packard Enterprise
Big Data is getting lots of press these days, but does it really apply to ASIC verification efforts? HPE has found that it does apply and can be instrumental in helping make smarter decisions. HPE is taking small steps to capitalize on the concept of Big Data. During this presentation, we will talk about our view of using Big Data concepts in the ASIC verification domain, using a few specific examples of how easy it is for the audience to get started with their own Big Data analysis. We will close with sharing our ideas on where we see larger Big Data opportunities being able to help our verification efforts in the future.
- Alan Pippin received his Bachelor of Science in Electrical Engineering from Brigham Young University and his Master of Science in Electrical Engineering from Colorado State University. He has been working in design and verification for 18 years. His experience spans across web design, systems IT support, database engineering, embedded software development, hardware design, and FPGA and ASIC design and verification. For the last 18 years, he has been at Hewlett Packard Enterprise where, as an Expert Technical Lead, he helps lead design and verification teams in delivering verified block IP. His lab develops ASIC chips for use in a variety of HPE products, including the HPE Superdome class of supercomputers and HPE’s Proliant servers. He is part of the engineering team that is developing technologies that are driving a new class of memory-driven Exascale Supercomputers.
“UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs” by Dave Burgoon, Microsoft
HLS (High-Level Synthesis) tools allow us to raise the level of abstraction of our hardware design models from RTL (Register Transfer Level) written in Verilog to a much higher, untimed level written in C++. These tools produce Verilog RTL models that are fed to conventional RTL-to-gates synthesis tools, the output of which flow into the physical design process. The advantages of working at this higher level of abstraction are well-documented. These include engineering productivity (e.g. fewer design coding errors), faster time to market, and the ability to quickly modify or leverage a design.
How are we to directly verify the source HLS model? Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog. This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.
- Dave Burgoon has a B.S. in Electrical Engineering, summa cum laude, from the University of Toledo, and an M.S. in Computer Science from Colorado State University. He has two U.S. patents, and has made various contributions over the years to industry conferences and publications, including DVCon, its predecessors (IVC/VIUF and HDLCon), DesignCon, and the Design Automation Conference. Supercomputers. Dave has over 36 years of experience in hardware design, verification, and functional modeling. He is presently a Senior Design Verification Engineer on Microsoft’s Custom Silicon Development team, which develops SoCs, chipsets, and sensors for Xbox, HoloLens, and other devices.
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