DVClub Austin – September 11, 2018 – Presenters: Mark Glasser (NVIDIA) & Aman Arora (NVIDIA)
Please join us on September 11, 2018 at the Norris Conference Center for a catered lunch and networking. Mark Glasser, a Principal Verification Architect at NVIDIA, and Aman Arora, a Verification Engineer at NVIDIA will be presenting.
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch / Presentations by Mark Glasser (NVIDIA) & Aman Arora (NVIDIA)
- 1:00pm — Networking
“Generic Programming in SystemVerilog” by Mark Glasser, NVIDIA
Making programs generic, or generic programming, means making programs independent of information about types, sizes, locations, and similar specific information. This requires certain programming styles and language features which avoids coding low-level details. SystemVerilog, with its heritage as a hardware modeling language, has some features for generic programming but is not considered a generic programming language.
We have developed the SystemVerilog Extension (SVX) library which provides facilities that improve the capability of SystemVerilog to render generic programs. SVX is written entirely in standard SystemVerilog with no reliance on DPI or any other external interface.
Aspects of generic programming are discussed, including removal of assumptions and abstraction.
We give a tour of the library and its facilities and features. Then we discuss concepts of generic programming in terms of SVX. Finally, we compare our work with others who have approached the same topic and describe some future directions for generic programming in SystemVerilog.
How are we to directly verify the source HLS model? Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog. This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.
- Mark Glasser has is currently a Principal Verification Architect at NVIDIA Corporation. His verification work includes such things as architecture of UVM-based testbenches, including multi-lingual, multi-abstraction testbenches, and verification of safety critical systems. His technical interests include tools and methodologies for verifying electronic systems. Mark holds a Bachelor of Science in Computer Science from California State University, Northridge.
“Using Hardware Verification Methodologies to Verify the BootROM of a Complex SoC” by Aman Arora, NVIDIA
The BootROM of an SOC is traditionally considered software and, hence, is verified by software teams. Since BootROM is fabricated as part of the SOC, and is therefore immutable after tape-out, functional errors have the potential to trigger a respin. To ensure functional correctness as early in the design cycle as possible, using hardware verification methodologies for BootROM verification can be of great help. These methods include constrained random stimulus generation, automated checking, and use of coverage tools to measure quality. The SystemVerilog constraint solver can be used for randomizing various boot configurations. A checker can observe events using monitors and ensure that the SOC is being configured correctly at each boot stage. Coverage can be obtained by parsing simulation logs and mapping it to disassembled boot code. During this presentation, we will talk through the implementation of these methods at a high level. We will share our experiences, as well as limitations and benefits of these techniques.
- Aman Arora is a verification engineer working at NVIDIA for the past 6 years. He has worked on a variety of verification roles including methodology, infrastructure, SOC level verification, unit level verification, and Silicon bring-up. He graduated from the University of Texas at Austin in 2012. He likes doing yoga, going on hikes, and listening to podcasts.
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