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DVClub Austin – June 28 – Presentations by Greg Smith, Oracle Corporation, “Functional Coverage is Useless!” and Stan Sokorac, ARM, “Optimizing Random Test Constraints Using Machine Learning Algorithms”


June 28, 2017


11:30 am - 01:30 pm

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DVClub Austin

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Norris Conference Center

2525 W Anderson Ln #365, Austin, TX 78757

Austin, TX, US, 78757

Please join us on June 28th at the Norris Conference Center for a catered lunch and networking. We will enjoy two presentations. The first is by Greg Smith of Oracle Corporation, and the second is by Stan Sokorac of ARM. Adnan Hamid of Breker Verification Systems will present the tutorial.

  • 11:30am—Doors Open / Networking

  • 12:00pm—Lunch / Presentation by Greg Smith, Oracle Corporation

  • 12:30pm—Presentation by Stan Sokorac, ARM

  • 1:00pm—Networking


Presentation One:

“Functional Coverage is Useless!” by Greg Smith, Oracle Corporation

Greg’s talk will observe the evolution in the use of coverage to measure verification completeness and tape out readiness.  His talk suggests that we are at an inflection point in the evolution of coverage where current methods are grossly inadequate.  He will suggest some directions in which coverage may evolve to meet the demands of today’s complex SOCs.

  • Greg Smith has been a verification engineer for all of his 30 year career. Processor verification has been the primary focus for nearly all of that time. Greg is a Director of Processor verification at Oracle/Sun where he has worked for the past 10+ years. Before that Greg worked at HP and Multiflow. Greg’s role at Oracle, besides managing the verification of next generation SPARC cores, is as a driver of innovation to devise new techniques to improve tape out quality and improve engineering efficiency. Greg is a passionate proponent of the use of metrics to measure verif efficiency and quality.


Presentation Two:

“Optimizing Random Test Constraints Using Machine Learning Algorithms” by Stan Sokorac, ARM

A staple of modern verification is constrained random simulation, which involves generation of random transaction streams controlled through a set of adjustable constraints. One of the major challenges of verification is finding the right combinations of constraints to produce the most stressful tests with the widest variety of random stimulus. With typical nightly and weekly regressions generating billions of simulation cycles in tens of thousands of tests, it is impossible for a human to process all available data. Verification engineers therefore use various aggregation and approximation methodologies, such as code and functional coverage, to gain insight into regression results. However, the fields of machine learning and data mining excel at exactly these kinds of problems by finding patterns in this vast repository of data and extrapolating insights to guide us in the best direction. This presentation describes a methodology in which coverage results and machine learning algorithms are used to generate tests most likely to find new bugs in a design.

  • Stan Sokorac is a Computer Engineering graduate from University of Toronto, and has worked at IBM, ATI, AMD, and ARM, in various roles including software development, ASIC design, verification, and management. He is currently a Sr. Principal Design Engineer at ARM, driving verification of the cache coherent memory subsystem on the next-generation ARM® Cortex-A® CPU core. He is passionate about introducing new methodologies and developing new flows that improve verification efficiency and effectiveness.


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