DVClub Presenters 2015-Present [20 YEARS of DVCLUB!!!]
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2025 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 7/31/2025 | Portland | Cliff Cummings | Paradigm Works, VP of Training | Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences |
| 7/30/2025 | Silicon Valley | Cliff Cummings | Paradigm Works, VP of Training | Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences |
| 7/24/2025 | RTP | Cliff Cummings | Paradigm Works, VP of Training | Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences |
| 7/23/2025 | Toronto | Gurinder Singh | Arm, Technical Director and DV Lead (Toronto) | GenAI for Chip Design: From PoCs to Production |
| 5/21/2025 | Austin | Ken Albin | System Semantics, Formal Design & Verification Technologist | Utilizing ISO-8601 to simplify DV scripting |
| 5/21/2025 | Austin | Moshe Vardi | Rice University, Distinguished Professor in Computational Engineering | Program Verification: a 75+-Year History |
| 3/26/2025 | Boston | Cliff Cummings | Paradigm Works, VP of Training | Sequencer Containers – A Unified and Simple Technique to Execute Both Sequences and Virtual Sequences |
2024 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/4/2024 | Austin/Ft Collins | Jean-Christophe Glas | Arm, Technical Director – Productivity Engineering | GenAI for Chip Design: From PoCs to Production |
| 9/4/2024 | Austin/Ft Collins | Ken Albin | Concurrent Systems, Consulting DV Engineer | Utilizing the Python Logging Library in your verification environment |
| 9/4/2024 | Austin/Ft Collins | Dan Joyce | Ericsson, Frontend Validation Lead | Gate Level Simulation – All my secrets to make it faster, easier, cheaper and more likely to find critical bug |
| 5/22/2024 | Boston | Henry Chang | Designer’s Guide Consulting, Inc, Vice President | Analog Modeling and Verification in a Digital World |
| 5/1/2024 | Austin/Ft Collins | Jean-Christophe Glas | Arm, Technical Director – Productivity Engineering | GenAI for Chip Design: From PoCs to Production |
| 3/28/2024 | Portland | Cliff Cummings | Paradigm Works, Vice President of Training and Sunburst Design, Founder | The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API |
| 3/28/2024 | Portland | Bill Moore | Paradigm Works, Senior Verification Engineer | Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM |
| 3/27/2024 | Silicon Valley | Cliff Cummings | Paradigm Works, Vice President of Training and Sunburst Design, Founder | The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API |
| 3/27/2024 | Silicon Valley | Bill Moore | Paradigm Works, Senior Verification Engineer | Gherkin Implementation in SystemVerilog Brings Agile Behavior-Driven Development to UVM |
2023 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/6/2023 | Austin | Cliff Cummings | Paradigm Works, Vice President of Training and Sunburst Design, Founder | The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API |
| 9/28/2023 | Austin/Ft Collins | Cliff Cummings | Paradigm Works, Vice President of Training and Sunburst Design, Founder | The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API |
| 4/19/2023 | Austin | Yash Phogat | Arm, Sr Engineer – ML | mL – Shrinking the Verification volume |
| 4/19/2023 | Austin | Ken Albin | System Semantics, Chief Engineer | The Top 5 Myths of Design Verification |
| 3/8/2023 | Boston | Cliff Cummings | Paradigm Works, VP of Training | The Untapped Power of UVM Resources and Why Engineers Should Use the uvm_resource_db API |
2022 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 10/21/2022 | North America (Virtual) | Madhu Iyer | Arm, Memory Subsystem Formal Verification Team | Formal Verification of the LoadStore Unit for A Class CPU cores at Arm Austin Design Center |
| 9/23/2022 | Austin/Ft Collins | Vivek Vedula | Arm, SDL Methodology Development for HW IPs Team Lead | Taming the Security Verification Beast: Arm’s Journey Through High-Performance CPUs |
| 9/23/2022 | Austin/Ft Collins | Cliff Cummings | Paradigm Works, VP of Training | Advanced UVM, Multi-Interface, Reactive Stimulus Techniques |
| 3/30/2022 | Austin/Ft Collins | Rahul Peddi | Arm, Senior Design Engineer | Accelerating the verification cycle of a Hyperscaler Compute Subsystem |
| 3/30/2022 | Austin/Ft Collins | Vaibhav Agrawal | Arm, CPU Formal Verification Team | Divide and Conquer: An overview of Formal verification strategy for CPUs designed at Arm in Austin |
2021 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| NO EVENTS IN 2021 | ||||
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/16/2020 | Austin/Ft Collins (Virtual) | Neil Johnson | Siemens/Mentor, DV Engineer | I’m Excited About Formal…My Journey From Skeptic To Believer |
| 12/16/2020 | Austin/Ft Collins (Virtual) | Cliff Cummings | Paradigm Works, VP of Training | UVM Message Display Commands – Capabilities, Proper Usage and Guidelines |
| 11/6/2020 | Silicon Valley and Portland (Virtual) | Neil Johnson | Siemens/Mentor, DV Engineer | I’m Excited About Formal…My Journey From Skeptic To Believer |
| 11/6/2020 | Silicon Valley and Portland (Virtual) | Cliff Cummings | Paradigm Works, VP of Training | UVM Message Display Commands – Capabilities, Proper Usage and Guidelines |
| 10/21/2020 | North America (Virtual) | Alan Pippin | Hewlett Packard Enterprise, MTS | A Silicon Design Lab’s Emulation Journey |
| 10/21/2020 | North America (Virtual) | Cliff Cummings | Paradigm Works, VP of Training | Two Techniques to Implement UVM Virtual Sequences |
| 9/25/2020 | Austin/Ft Collins (Virtual) | Harry Foster | Siemens/Mentor, Chief Scientist Verification for the Design Verification Technology Division | The 2020 Wilson Research Group Functional Verification Study |
| 9/25/2020 | Austin/Ft Collins (Virtual) | Cliff Cummings | Paradigm Works, VP of Training | UVM Reactive Stimulus Techniques |
| 8/21/2020 | Silicon Valley and Portland (Virtual) | Mark Glasser | Cerebras Systems, Verification Architect | 10 Things You Did Not Know are in UVM |
| 8/21/2020 | Silicon Valley and Portland (Virtual) | Cliff Cummings | Paradigm Works, VP of Training | UVM Reactive Stimulus Techniques |
| 7/15/2020 | Boston and RTP(Virtual) | Michael Bode | Arm, Design Engineer | How Design Verification Fits into a Functionally Safe World |
| 7/15/2020 | Boston and RTP(Virtual) | Ray Salemi | Siemens/Mentor, FPGA/MilAero Solutions Manager | Correct by Design: Catch Your Design Bugs Before Simulation |
| 7/15/2020 | Boston and RTP(Virtual) | Cliff Cummings | Paradigm Works, VP of Training | UVM Reactive Stimulus Techniques |
| 6/30/2020 | Austin/Ft Collins (Virtual) | Jeremy Ridgeway | Broadcom, DV Lead | Wait a sec, I’m not quite done! Delay $finish from every `uvm_fatal report message |
| 6/30/2020 | Austin/Ft Collins (Virtual) | Mark Glasser | Cerebras Systems, Verification Architect | Generic Programming in SystemVerilog |
| 6/30/2020 | Austin/Ft Collins (Virtual) | Alan Pippin | Hewlett Packard Enterprise, MTS | A Silicon Design Lab’s Emulation Journey |
| 5/15/2020 | Silicon Valley (Virtual) | Dave Rich | Siemens/Mentor, Member of the Flows and Methodology Product Engineering team | SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results |
| 5/15/2020 | Silicon Valley (Virtual) | Michael Bode | Arm, Design Engineer | How Design Verification Fits into a Functionally Safe World |
| 4/17/2020 | Austin/Ft Collins (Virtual) | Rich Edelman | Siemens/Mentor, DV Technologist | COVERGATE: Coverage Exposed |
| 4/17/2020 | Austin/Ft Collins (Virtual) | Michael Bode | Arm, Design Engineer | How Design Verification Fits into a Functionally Safe World |
| 2/21/2020 | Toronto | Neil Johnson | Siemens/Mentor, DV Engineer | Remain Agile Under Pressure with Test-Driven Development |
| 2/21/2020 | Toronto | Cliff Cummings | Paradigm Works, VP of Training | SystemVerilog Assertions – Bindfiles & Best Known Practices for Simple SVA Usage |
| 2/5/2020 | Silicon Valley | Dave Rich | Mentor, a member of the Flows and Methodology Product Engineering team | SystemVerilog Random Constraints Demystified |
| 2/5/2020 | Silicon Valley | Cliff Cummings | Sunburst Design, President | UVM Virtual Sequence Techniques |
2019 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/11/2019 | Austin | Ken Matthews
and Ashutosh Moghe |
Samsung, Sr Staff Engineer
Qualcomm, Staff Verification Engineer |
Verification of a Modern Branch Predictor |
| 12/11/2019 | Austin | Xiushan Feng | Samsung, Formal Verification Group Lead | Sequential Equivalence Checking Beyond Clock Gating |
| 11/8/2019 | Silicon Valley | James Gorman | Ericsson, System Lead/Architect | What is 5G |
| 11/8/2019 | Silicon Valley | Glenn Canto | Ericsson, Virtual Platforms Engineer | Effective Reuse Through Virtual Platforms at Ericsson |
| 11/8/2019 | Silicon Valley | Rich Edelman | Siemens/Mentor, Verification Technologist | UVM – Where Are We? Is it Safe? |
| 10/18/1019 | Boston | Tom Fitzpatrick | Siemens/Mentor, Strategic Verification Arhcitect | Agile Regression Management |
| 10/18/1019 | Boston | Seán Adam | AFL. Vice President of Market Strategy and Innovation | 5G in 5 Minutes |
| 10/18/1019 | Boston | Cliff Cummings | Sunburst Design, President | Using UVM Virtual Sequencers & Virtual Sequences |
| 9/27/2019 | Austin | James Gorman | Ericsson, System Lead/Architect | What is 5G |
| 9/27/2019 | Austin | Glenn Canto | Ericsson, Virtual Platforms Engineer | Effective Reuse Through Virtual Platforms at Ericsson |
| 9/27/2019 | Austin | Rich Edelman | Siemens/Mentor, Verification Technologist | UVM – Where Are We? Is it Safe? |
| 8/8/2019 | RTP | Tom Fitzpatrick | Siemens/Mentor, Strategic Verification Arhcitect | Portable Stimulus: Evolution to Revolution (a.k.a. Don’t Panic) |
| 7/31/2019 | Boston | Tom Fitzpatrick | Siemens/Mentor, Strategic Verification Arhcitect | Portable Stimulus: Evolution to Revolution (a.k.a. Don’t Panic) |
| 7/10/2019 | Silicon Valley | Kurt Shuler
and Diego Botero |
Arteris IP, VP and Functional Safety Manager
Arteris, Functional Safety Engineer and Corporate Application Engineer |
Maintaining ISO 26262 Activities into the SoC Verification Flow |
| 6/27/2019 | Fort Collins | Dave Burgoon
and Mike Erickson |
Microsoft, Senior Design Verification Engineer
Microsoft, Principal Engineer |
UVM for IP Designers: Moving Toward “Killing two birds with one stone |
| 6/27/2019 | Fort Collins | Cliff Cummings | Sunburst Design, President | UVM Analysis Port Functionality and Using Transaction Copy Commands |
| 6/19/2019 | Austin | Elena Tsanko | IBM, Processor Validation Engineer | Portable Address Translation Stimuli Gneration Using Graph-Based CSP |
| 6/19/2019 | Austin | Cliff Cummings | Sunburst Design, President | UVM Analysis Port Functionality and Using Transaction Copy Commands |
| 6/13/2019 | Portland | Cliff Cummings | Sunburst Design, President | UVM Analysis Port Functionality and Using Transaction Copy Commands |
| 5/29/2019 | Boston | Jeremy Ridgeway | Broadcom, PCI-Express subsystem level verification team | Want Functional Coverage Closure? Don’t Kneel Before the Almighty Random Constraint Solver |
| 4/24/2019 | Silicon Valley | Mark Glasser | NVIDIA, Principal Verification Engineer | Multi-domain Simulation |
| 4/24/2019 | Silicon Valley | Cliff Cummings | Sunburst Design, President | UVM Analysis Port Functionality and Using Transaction Copy Commands |
| 3/20/2019 | Austin | Harry Foster | Siemens/Mentor, Chief Scientist Verification | Industry Trends in Functional Verification |
| 1/25/2019 | Silicon Valley | Amol Bhinge | NXP, Director | FPGA-based Emulation: Selecting the Right Platform |
2018 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/7/2018 | Austin | Nick Jones | Samsung, Verification Engineer | Leveraging LevelDB for Unit-level Replay of Top-level Stimulus in UVM |
| 12/7/2018 | Austin | Sean Sun | Global HW Performance Verification Manager | A New Frontier of Verification |
| 11/7/2018 | Boston | Cliff Cummings | President of Sunburst Design, Inc. | UVM Analysis Port Functionality and Using Transaction Copy Commands” |
| 10/10/2018 | Silicon Valley | Mark Glasser | NVIDIA, Principal Verification Architect | Generic Programming in SystemVerilog |
| 9/11/2018 | Austin | Mark Glasser | NVIDIA, Principal Verification Architect | Generic Programming in SystemVerilog |
| 9/11/2018 | Austin | Aman Arora | NVIDIA, Verification Engineer | Using Hardware Verification Methodologies to Verify the BootROM of a Complex SoC |
| 8/2/2018 | RTP | Erik de Briae | Verification Manager at Netronome | ROSE DV Tool Suite |
| 8/2/2018 | RTP | Josh Rensch | SoC Verification Lead at GlobalFoundries | Team Building is as Easy as Stealing a Car |
| 8/1/2018 | Boston | Dave Burgoon | Senior Design Verification Engineer at Microsoft | UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs |
| 8/1/2018 | Boston | Narayana Reddy | Senior Application Engineer at Cadence | Cross-Domain Merging of Simulation and Emulation Coverage Databases (Tutorial) |
| 7/11/2018 | Silicon Valley | Dave Burgoon | Senior Design Verification Engineer at Microsoft | UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs |
| 7/11/2018 | Silicon Valley | Josh Rensch | SoC Verification Lead at GlobalFoundries | Team Building is as Easy as Stealing a Car |
| 6/19/2018 | Austin | Swami Venkatesan | Senior Architect at Cadence | Accellera Portable Stimulus Specification Explained |
| 6/19/2018 | Austin | Dave Burgoon | Senior Design Verification Engineer at Microsoft | UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs |
| 5/9/2018 | Boston | Josh Rensch | SoC Verification Lead at GlobalFoundries | Team Building is as Easy as Stealing a Car |
| 5/9/2018 | Boston | Erik de Briae | Verification Manager at Netronome | ROSE DV Tool Suite |
| 4/27/2018 | Fort Collins | Amol Bhinge | Design Verification and Emulation Director at NXP | SoC Design Verification: Challenges, Innovations and Beyond |
| 4/27/2018 | Fort Collins | Alan Pippin | Expert Technical Lead at Hewlett Packard Enterprise | Big Data in Verification: Making Your Engineers Smarter |
| 4/27/2018 | Fort Collins | Dave Burgoon | Senior Design Verification Engineer at Microsoft | UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs |
| 4/19/2018 | Portland | Matan Vax | Senior Architect at Cadence Design Systems | Accellera Portable Stimulus Specification ExplainedPerspec System Verifier and Portable Stimulus Standard in Action (Tutorial) |
| 4/17/2018 | Silicon Valley | Matan Vax | Senior Architect at Cadence Design Systems | Accellera Portable Stimulus Specification ExplainedPerspec System Verifier and Portable Stimulus Standard in Action (Tutorial) |
| 3/21/2018 | Austin | David Borland | Director of Silicon Optimizations at Amazon | EDA in the Cloud |
| 3/21/2018 | Austin | Kaushik Gopalakrishnan | Senior Design Engineer at ARM | Anvil – Multicore Memory Subsystem Verification Tool for Top-Level DV |
2017 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/6/2017 | Austin | John Dickol | Principal Engineer at the Samsung | I Didn’t Know Constraints Could Do That! |
| 12/6/2017 | Austin | Heath Chambers | President of HMC Design Verification, Inc | SystemVerilog and UVM Virtual Interfaces for Class-Based Testing (Tutorial) |
| 11/8/2017 | Boston | Greg Smith | Verification Engineer at Oracle Corporation | Functional Coverage is Useless |
| 10/11/2017 | Silicon Valley | Greg Smith | Verification Engineer at Oracle Corporation | Functional Coverage is Useless” by Gr |
| 10/11/2017 | Silicon Valley | Andy Stein | VP of Sales at Avery Design Systems | Improving ‘Gate Simulation Signoff’ throughput by handling the noise from False X’s” by Andy Stein, Avery Design Systems (Tutorial) |
| 9/13/2017 | Austin | Vikram Khosa | Verification Lead at ARM | Deep-Formal Deployment on an A-class ARM CPU Family : An Overview and Lessons Learned |
| 9/13/2017 | Austin | Vaibhav Agrawal | Validation Engineer at ARM | Two Case Studies in Formal Deployment on ARM CPUs: Instruction-Fetch and Floating Path Datapath |
| 6/28/2017 | Austin | Greg Smith | Verification Engineer at Oracle Corporation | Functional Coverage is Useless!” by Greg Smith |
| 6/28/2017 | Austin | Stan Sokorac | Sr. Principal Design Engineer at ARM | Optimizing Random Test Constraints Using Machine Learning Algorithms |
| 6/8/2017 | Portland | Cliff Cummings | President of Sunburst Design, Inc. | SystemVerilog Assertions – Bindfiles & Best Known Practices for Simple SVA Usage |
| 5/24/2017 | Silicon Valley | Eldon Nelson | Verification Engineer at Intel | Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation |
| 5/24/2017 | Boston | Adnan Hamid | CEO, Breker Verification Systems | Portable Stimulus with Breker’s TrekSoC tool (Tutorial) |
| 5/17/2017 | Boston | Cliff Cummings | President of Sunburst Design, Inc. | SystemVerilog Assertions – Bindfiles & Best Known Practices for Simple SVA Usage |
| 5/17/2017 | Boston | Adnan Hamid | CEO, Breker Verification Systems | Portable Stimulus with Breker’s TrekSoC tool (Tutorial) |
| 4/5/2017 | Raleigh | Amol Bhinge | Senior SoC Verification Manager at NXP Semiconductors | SoC Design Verification: Challenges, Innovations and Beyond |
| 3/8/2017 | Austin | Nihar Shah | ARM | Detoxify Your Schedul With A Low-Fat UVM Environment |
| 3/8/2017 | Austin | Prasad Saravu | Verification Lead, Samsung | Multi-Processor Memory Scoreboard: A multi-processor memory ordering and data consistency checker |
| 3/8/2017 | Austin | Adnan Hamid | CEO, Breker Verification Systems | Portable Stimulus with Breker’s TrekSoC too (Tutorial) |
| 2/23/2017 | Fort Collins | Cliff Cummings | President of Sunburst Design, Inc. | SystemVerilog Assertions – Bindfiles & Best Known Practices for Simple SVA Usage |
| 2/23/2017 | Fort Collins | Jeremy Ridgeway | Principal Verification Engineer at Broadcom | The Objectification of SystemVerilog Constraints |
| 2/23/2017 | Fort Collins | Matt Diehl | Applications Engineer with Cadence Design Systems | Next Generation Verification Planning and Management Solution Overview (vManagerTM) (Tutorial) |
| 1/11/2017 | Silicon Valley | Cliff Cummings | President of Sunburst Design, Inc. | SystemVerilog Assertions – Bindfiles & Best Known Practices for Simple SVA Usage |
| 1/11/2017 | Silicon Valley | Andy Stein | VP of Sales at Avery Design Systems | Gate Simulation signoff throughout by handling the noise from False X’s (Tutorial) |
2016 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/7/2016 | Austin | Thinh Ngo | Principal Design Verification Engineer at Broadcom | Accelerate Your Testbench Development Time With a Hybrid Testbench |
| 12/7/2016 | Austin | Eldon Nelson | Verification Engineer at Intel | “Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 |
| 12/7/2016 | Austin | Sasa Stamenkovic | Application Engineer at OneSpin Solutions | Making Formal Friendly for Simulation Savvy Engineers (Tutorial) |
| 12/7/2016 | Austin | Rayfes Mondal | ARM | Virtual Prototyping with ARM SoC Designer for IP Selection and Architectural Exploration (Tutorial) |
| 12/7/2016 | Austin | Venkataramana “Reddi” Reddipalli | Applications Engineer at Cadence | High-Speed Software-Driven SoC Verification with Parallel Simulation (Tutorial) |
| 11/9/2016 | Boston | Dave Brownell | Design Verification Methodology Manager at Analog Devices | Portable Stimulus: The Next Step in Verification Productivity |
| 11/9/2016 | Boston | Franco De Seta | Applications Engineer, Cadence | Measuring SoC Performance: How to create SoC performance use cases with Cadence’s Interconnect Workbench (IWB) (Tutorial) |
| 10/12/2016 | Silicon Valley | Dave Brownell | Analog Devices, Design Verification Methodology Manager | Portable Stimulus: The Next Step in Verification Productivity |
| 10/12/2016 | Silicon Valley | Sven Beyer
and Sasa Stamenkovic |
Technical Manager at OneSpin
Application Engineer at OneSpin |
Making Formal Friendly for Simulation Savvy Engineers (Tutorial) |
| 9/7/2016 | Austin | Ken Albin | Oracle, Senior Design Verification Engineer | The Cost of SoC Bugs |
| 8/24/2016 | Boston | John Dickol | Principal Engineer at Samsung’s Austin R&D Center (SARC) | Advanced Usage Models for Continuous Integration in Verification Environments |
| 7/27/2016 | Silicon Valley | Amol Bhinge | NXP, Senior Verification Manager | SoC Design Verification: Challenges, Innovations and Beyond |
| 6/15/2016 | Portland | Amol Bhinge | NXP, Senior Verification Manager | SoC Design Verification: Challenges, Innovations and Beyond |
| 6/1/2016 | Austin | Zhipeng Ye | TI, Senior Verification Engineer | Functional Coverage Collection for Analog Circuits |
| 6/1/2016 | Austin | Stan Sokarac | ARM, Senior Principal Design Engineer | SystemVerilog Interface Classes: More Useful Than You Thought |
| 5/18/2016 | Boston | Eldon Nelson | Intel, Verification Lead | Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012 |
| 4/27/2016 | Silicon Valley | Cliff Cummings | Sunburst Design, CEO | Using UVM Virtual Sequencers & Virtual Sequences |
| 4/27/2016 | Silicon Valley | Roxan Saint-Hilaire | Cadence, AE Director | New Debug Methodology for UVM – a tutorial (Tutorial) |
| 4/7/2016 | RTP | William Joyner | SRC, Senior Science Director | SRC: Battling Bugs Since 1982 |
| 4/7/2016 | RTP | Herbert Rivera-Sanchez | Cadence, Solutions Architect | SoC Performance Analysis through the use of VIPs (Tutorial) |
| 3/9/2016 | Austin | Xiankun “Robert” Jin | NXP, Senior Verification Engineer | A Built-in-Self-Test Solution of Analog-to-Digital Converter Benefiting from High Level Synthesis |
| 3/9/2016 | Austin | Bruno Bratti | Wave Semiconductor, Application Engineer | AXI HW/SW Verification for FPGA |
| 2/17/2016 | Boston | Bruno Bratti | Wave Semiconductor, Application Engineer | AXI HW/SW Verification for FPGA |
| 1/27/2016 | Portland | Bruno Bratti | Wave Semiconductor, Application Engineer | AXI HW/SW Verification for FPGA |
| 1/20/2016 | Toronto | Bruno Bratti | Wave Semiconductor, Application Engineer | AXI HW/SW Verification for FPGA |
| 1/13/2016 | Silicon Valley | Ram Narayan
and Tom Symons |
Senior Verification Engineers, Oracle Labs’ Hardware Adv. Development Group | I Created the Verification Gap |
2015 |
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Date |
Location |
Presenter |
Company, Title/Role |
Topic |
| 12/2/2015 | Austin | Ram Narayan
and Tom Symons |
Senior Verification Engineers, Oracle Labs’ Hardware Adv. Development Group | I Created the Verification Gap |
| 12/2/2015 | Austin | Magdy El-Moursy and Ashraf Salem | Mentor Graphics in Egypt | The Virtual Platform technology for Electronic System Level Design and Verification (Tutorial) |
| 11/11/15 | Boston | Suckheui Chung | AMD,Verification Engineer | 100% Functional Coverage with Formal Methodology |
| 10/14/15 | Silicon Valley | Bruno Bratti | Wave Semiconductor, Application Engineer | AXI HW/SW Verification for FPGA |
| 10/7/15 | RTP | Oleg Petlin | AMD, Senior Manager | Formal property verification at AMD: Theory and Practice |
| 9/9/15 | Austin | Eric Hennenhoefer | DVClub Founder | 10-year Anniversary Celebration – Panel of Guest Speakers |
| 8/12/15 | Boston | John Sweeney | Cavium, Senior Consulting Engineer | Distributed Bottoms Up Project Planning and Tracking |
| 8/12/15 | Boston | Monica Farkash | NXP Austin, R&D, Design Enablement | HW Development with Data Mining: Understanding Coverage |
| 7/15/15 | Silicon Valley | John Dickol | Samsung Austin R&D Center (SARC). | Advanced Usage Models for Continuous Integration in Verification Environments |
| 6/25/15 | Portland | Ed Nolan | Teradyne, Principal Engineer | PCIe Based Communication Verification Infrastructure |
| 6/3/2015 | Austin | John Dickol | Samsung, Principal Engineer | Advanced Usage Models for Continuous Integration in Verification Environments |
| 5/13/15 | Boston | Mark Glasser | NVidia, Verification Manager | Configuration in UVM: The Missing Manual |
