Narasimha Karunakar, Engineer - Qualcomm


Low Power Design Verification of Complex Chips - pdf


  • Narasimha Karunakar received his degree with honors from Kuvempu Vishwavidyanilaya in Electronics and Communications
  • Narasimha has presented a paper on “RTL and Verification Challenges and Changes for Low Power Design Verification Using MVSIM” at Snug Bangalore 2009 (Synopsys).
  • Before becoming an engineer at Qualcomm, Narasimha was involved in DDR3 Controller verification at SOC level for AMD for over five years.
  • He was also a Verification Lead at Wipro Technologies, where he led a team which worked on functional verification of storage controller chips and their boards using C/C++ for EMC2.

Ravi P Gupta, VLSI Design Engineer - STMicroelectronics

 Coverage Solutions on Emulators - pdf


  • Ravi Gupta is currently a design engineer working on Emulators (Extreme, PxP) and TLM based verification environment with SCE-MI standard.
  • He earned his degree in Electronics and Communication from Sikkim Manipal University of Health, Medical and Technological Sciences.
  • Ravi was previously employed as a Design Verification Engineer at Blueberry Chip Design Services, where he completed and delivered modules including an SG-DMA and AXI master/slave interface. Here, he also successfully completed project at DRDO lab in Bangalore.

Sandeep Jana, Technical Lead - STMicroelectronics

 TLM Based Software Control of UVCs for Vertical Verification Reuse - pdf


  • Sandeep Jana is the Technical Lead for STMicroelectronics, where he was awarded the 2011 Q1 Quarterly Project Award for excellent execution of project for a customer division.
  • He earned his degree from the YMCA Institute of Engineering in Electronics Instrumentation and Controls, and graduated with a Gold Medal awarded by the Governor of the State.
  • Sandeep has been published in TechOnline India and CDNLive 2010 for his work in system level verification.
  • During his tenure at HCL Technologies, he worked on customer projects for CoWare (now Synopsys) in the services team.

Mehul Kumar, Design Verification Engineer - Qualcomm

 Testbench Linter: Automated Rule Checker Framework for Testbenches - pdf


  • Mehul Kumar is currently employed by Qualcomm, where he works on Sub-System and Chip level verification for Peripherals for eg. USB, SPI, I2C, etc.
  • He has been published in, Defensive Publication, EETimes, and the International Journal of Electronics and Communication Technology (IJECT) for his work on testbenches.
  • After serving as Project Manager at Perfectus Inc. for two years, Mehul was a Senior Design Engineer at Freescale, and worked on verification of various IPs at block level for a SOC, which includes Functional Model designs, verification environment, writing Test Plans and Testcases in UVM.
  • He also worked on the design and verification teams at Microchip Technology and nSys Design Systems.

Nitin Goel, Senior Design Engineer - Freescale Semiconductor

 Novel Approach for Accelerating Mixed Signal Verification - pdf

  • Nitin Goel is the Senior Design Engineer at Freescale Semiconductor India, working in the Automotive Microcontroller Group (AMCG) for over six years.
  • He graduated from Netaji Subhash Institute of Technology, Delhi in 2006.
  • Since then, he has been in the frontend verification domain. Along with experience in IP Level, SoC Level, and Core Verification, he has been working in Tester pattern development and debugging.

Zihno Jusufovic, Verification Engineer - AMD

Jaguar x86 Core Functional Verification - pdf

  • Zihno Jusufovic is the technical lead on the Jaguar x86 core testbench at AMD.
  • He has over 10 years of experience in verification of x86 processors, RISC processors and SOCs.
  • Additionally, Zihno holds patents in Reducing Stalls in a Processor Pipeline and Updating Instruction Fault Status Register.
  • Zihno earned his B.S. and M.S. in Electrical Engineering from The University of Texas at Arlington.