Ken Albin, Verification Methodologist


Populations, Variety and Selection: Verifying Complex Designs - pdf


  • Ken Albin is an independent consultant based out of Austin, Texas specializing in verification methodology and design flow analysis.
  • After earning an MSEE degrees at Kansas State University, Ken worked in the Processor Technology department at Rockwell-Collins in Cedar Rapids, Iowa; formal verification research firm Computational Logic Inc; on advanced verification tools and methodology at Motorola/Freescale Semiconductor, and at AMD focusing on verification methodology.
  • Ken has been working in design verification since before they called it design verification.

Eric Deal, President - Cyclic Design


SystemVerilog Assertions (SVA) in the Design/Verification Process - pdf


  • Eric is the founder and President of Cyclic Design, a silicon IP/consulting company specializing in error correction solutions for NAND flash.
  • He has 18 years digital logic design and architecture experience at companies such as IBM, Rockwell/Conexant, Sigmatel, and Multixtor.
  • Eric has helped develop several SOC platforms and has experience with error correction (ECC), encryption, security, image processing, system bus, clocking, and I/O interfaces.
  • He promoted the use of OVL assertions while at Conexant and was an early adopter of SystemVerilog assertions while at Sigmatel.
  • Eric has a Bachelor's Degree in Electrical Engineering from Texas A&M University.

Jing Li, Verification Manager - Broadcom


  • Jing is Senior Manager of Verification in Broadcom’s Network Switching group.
  • She has over 10 years of experience in various areas of verification including block level, chip level, Formal and verification methodology.
  • She has a BSEE from UC Berkeley and MSEE from Stanford.

James Roberts, Sr. Verification Engineer - Oracle


RDBMS-based Coverage Collection and Analysis - pdf


  • James Roberts is a Senior Verification Engineer in UltraSparc design at Oracle (formerly Sun).
  • Prior to Sun, he worked at Intel as a Circuit Design Engineer and Verification Engineer.
  • He also worked on physical verification and custom design at a couple other companies, including  Freescale in Austin.
  • Mr. Roberts holds an MSEE from Georgia Tech, and is a card-carrying Yellowjacket.

Greg Smith, Sr. Verification Manager - Oracle

Verification Bug Metrics: A Different Approach - pdf

  • Greg Smith has over 25 years of experience in the design of processors, ASICs and full systems.
  • Greg Smith is currently a Senior Manager of Design Verification for SPARC cores at Oracle - a position he has held for 5 years.
  • Prior to Oracle, Greg managed the design and verification of fault tolerant ASIC designs for Tandem Computers. It was at Tandem/HP that Greg developed a passion for metrics as a tool for determining design quality and completion which lead to the tape out of a dozen ASICs each of which had first pass success.
  • Prior to Tandem Greg was managing the development of a VLIW mini-supercomputer system at a  
    company called MultiFlow in  New Haven, Connecticut.
  • Greg started his career designing minicomputer systems at Prime Computer in Natick, Mass.
  • Greg holds a BSCS from Ohio Sate and bleeds scarlet and gray.

Tim Stremcha, Sr. Design Engineer - Open Silicon

Formal Methods for Verifying Complex Designs - pdf


  • Tim Stremcha has more than 20 years of experience designing leading edge IC's and systems.
  • He began his career in the high performance computing (HPC) realm at Cray Research and SGI.
  • Since then he has worked for a design services enterprise that has served a broad range of market segments focused on aggressive design challenges.