Dr. Jeremy Bennett, Founder & CEO - Embecosm

Processor verification using open source tools and the GCC regression test suite: A case study - pdf

  • Embecosm was founded by Dr Jeremy Bennett, an expert on hardware modeling and embedded software development.
  • Prior to founding Embecosm, Dr Bennett was Vice President of ARC International plc, following their acquisition of Tenison Design, developers of the VTOC tool set for cycle accurate modeling of SoC hardware, where he had been CEO and CTO.
  • Before moving into industry in the mid-1990's, Dr Bennett pursued academic research into computer architecture, modeling and compiler technology at Cambridge and Bath Universities in the UK.
  • He is author of numerous academic papers as well as the popular textbook "Introduction to Compiling Techniques" (McGraw-Hill 1990, 1995, 2003).
  • Dr Bennett holds an MA and PhD in Computer Science from Cambridge University.
  • He is a Member of the British Computer Society, a Chartered Engineer and a Chartered Information Technology Professional.

Prabhu Bhairi - Texas Instruments Bangalore

Approaches for Power Management Verification of SoC Having Dynamic Power and Voltage Switching - pdf

  • Currently working as Verification manager of OMAP SoC’s in Texas instruments India. Responsible for overall SoC verification of OMAP chips and specialized in low power verification domain
  • Working in Texas instruments from past 7 years, have lead several SoC verification activities. The designs worked are mainly targeted to Mobile handset application processing and modems
  • Have about 10 years of working experience in VLSI mainly on in the front end design and verification domain. Currently staff member of technical group in Texas instruments
  • Prior to joining TI, worked in Wipro Technology as Senior Design engineer
  • B.E. in PDA from college of engineering, Gulbarga

Bob Colwell, Fellow (retired) - Intel

The Validation Attitude - pdf

  • Bob Colwell was Intel's chief IA32 (Pentium) microprocessor architect from 1992-2000, and managed the IA32 Architecture group at Intel's Hillsboro, Oregon facility through the P6 and Pentium 4 projects.
  • He was named the Eckert-Mauchly award winner for 2005, the highest honor in the field of computer architecture, for "outstanding achievements in the design and implementation of industry-changing microarchitectures, and for significant contributions to the RISC/CISC architecture debate."
  • He was elected to the National Academy of Engineering in 2006 "for contributions to turning novel computer architecture concepts into viable, cutting-edge commercial processors".
  • He was named an Intel Fellow in 1996, and an IEEE Fellow in 2006. Previously, Colwell was a CPU architect at VLIW minisupercomputer pioneer Multiflow Computer, a hardware design engineer at workstation vendor Perq Systems, and a member of technical staff at Bell Labs.
  • He has published many technical papers and journal articles, is inventor or co-inventor on 40 patents, and has participated in numerous panel sessions and invited talks.
  • He is the Perspectives editor for IEEE Computer Magazine, wrote the At Random column 2002-2005, and is author of The Pentium Chronicles, a behind-the-scenes look at modern microprocessor design.
  • He is currently an independent consultant.
  • Colwell holds the BSEE degree from the University of Pittsburgh, and the MSEE and PhD from Carnegie Mellon University.

Allison Goodman - Intel

Tales from the Trenches: Validation Missteps Making Us Full-Time Firefighters- pdf

  • Allison Goodman is a validation program manager at Intel for their new client and enterprise solid state hard drives.
  • Prior to her current position, she has been a validation engineer working on several of Intel’s products and also a technical project manager in the laptop product group.
  • Allison earned her B.S. in computer and electrical engineering from Cornell University and is PMP certified.
  • She is a Lt. Governor for the Society of Women Engineers and also a master instructor at Intel for Project and Product Risk Management.

Chitlesh Goorah, Digital Design Engineer - ON Semiconductor

Free Electronic Lab: Hardware engineering made easy - pdf

  • Chitlesh Goorah is the Free Electronic Lab founder. He works at ON Semiconductor as a Digital Design Engineer and holds a master degree in Micro-Nano Electronics engineering.
  • In his leisure time, he strives to keep the FEL in pace as an advance electronic design and simulation platform.
  • Interoperability is one of his main targets for the success of the EDA community and works hand-in-hand with many upstream EDA developers.

John M. Ludden - IBM

Mainline Functional Verification of IBM's POWER7 Processor Core- pdf

  • John Ludden is a senior technical staff member at IBM where he has over 18 years of experience in design verification spanning mainframes, x86 and PowerPC processor based systems.
  • He has been the architecture verification lead engineer for IBM's POWER3/4/5/6 processors and is a member of IBM's Verification Advisory Team. For the past 14 years,
  • John has worked with IBM's test generation research team in Haifa, Israel to improve instruction-level test generation capabilities in order to address out-of-order execution, symmetric multi-processing and simultaneous multi-threading (SMT) processor verification requirements.
  • John received a Corporate Award from IBM for his leadership in defining and executing the POWER5 SMT verification plan.
  • He has co-authored three papers and currently holds two patents in microprocessor verification.
  • John received his BSEE from the Rochester Institute of Technology in Rochester, New York in 1990.

Rich Porter - Art of Silicon

Architecture For Massively Parallel HDL Simulationy - pdf

  • Rich Porter is Technical Director of Art of Silicon, a silicon IP and consultancy company which he co-founded in 2005.
  • Rich has been in the industry for 15 years and previously worked at Element-14 and STMicroelectronics.
  • Rich spent the early part of his career creating maintainable and reusable RTL, subsequently he has been involved in verification.
  • His interests include bringing these two disciplines together by specifying design features that aid the verification process.

Krishnaraj Rao - nVidia

  • Krishnaraj Rao is currently working as a Sr. Engineering Manager at Nvidia, responsible for design & development of IPs that go into Nvidia products.
  • He has been at Nvidia for the past 12 years, and has worked on GPUs as well as managed Chipset products and IP Groups.
  • Prior to Nvidia, he worked for 4 years at Weitek and Rockwell Semiconductors in areas of 2D Graphics, Video & Displays.
  • He has a BSEE from Mangalore University and an MSEE from Louisiana State University.
  • Krishnaraj has filed for 11 patents in the field of Graphics and Display subsystems, of which 5 have been issued.

 

James Roberts, Sr. Verification Engineer - Oracle

 

High Performance Collection of Coverage Metrics Using a Relational Database Backend - pdf

 

  • James Roberts is a Senior Verification Engineer in UltraSparc design at Oracle (formerly Sun).
  • Prior to Sun, he worked at Intel as a Circuit Design Engineer and Verification Engineer.
  • He also worked on physical verification and custom design at a couple other companies, including  Freescale in Austin.
  • Mr. Roberts holds an MSEE from Georgia Tech, and is a card-carrying Yellowjacket.

Nirajnayan Sharma - Bluespec

Emulation on Your Desktop - pdf

  • Nirajnayan Sharma heads Bluespec's Engineering and Marketing operations in India and is based out of Bangalore. Bluespec supplies the global electronics market with tool-sets, and IP leveraging the industry's high-level synthesis solution that embraces system, control, algorithmic, and verification IP
  • Niraj has worked in the VLSI space for close to 10 years.
  • Prior to Bluespec, he held positions in architecture, design, and verification at Analog Devices, Intel, and National Semiconductor.
  • Niraj is a B.Tech. in Electronics and Electrical Communication Engineering from IIT Kharagpur

Michael Sims - NASA

  • Michael Sims is Research Scientist in the Intelligent Systems Division of NASA Ames, Co-Investigator on the Mars Exploration Rovers (MER), Deputy Chief Scientist for NASA Engineering and Safety Center and cofounder of the Center for Collaboration Science and Applications (CCSA, http://www.cmu.edu/silicon-valley/ccsa/).
  • Michael received a BS in Physics and a Ph.D. in Computer Science and Mathematics from Rutgers University and has been at NASA Ames Research Center since 1987.
  • His research includes robotics, machine learning, visualization, and tools for enhancing and easing scientific modeling and collaboration.
  • Previously he served as agent for artificial intelligence, robotics and human factors for NASA’s missions beyond low Earth orbit in the Office of Exploration.
  • Michael is actively involved in plans for future planetary missions including robotic activities and human settlements on the Mars and the Moon.
  • On the MER mission, in addition to being Long Term Planning Lead, for 7 of MER’s 9 camera he serves as payload uplink lead and designed and built the software system which is used on each rover for automating most of that work.

Greg Smith, Sr. Verification Manager - Oracle

Using Bug Arrival Rates to Predict the Future - pdf

 

  • Greg Smith has over 25 years of experience in the design of processors, ASICs and full systems.
  • Greg Smith is currently a Senior Manager of Design Verification for SPARC cores at Oracle - a position he has held for 5 years.
  • Prior to Oracle, Greg managed the design and verification of fault tolerant ASIC designs for Tandem Computers. It was at Tandem/HP that Greg developed a passion for metrics as a tool for determining design quality and completion which lead to the tape out of a dozen ASICs each of which had first pass success.
  • Prior to Tandem Greg was managing the development of a VLIW mini-supercomputer system at a  
    company called MultiFlow in  New Haven, Connecticut.
  • Greg started his career designing minicomputer systems at Prime Computer in Natick, Mass.
  • Greg holds a BSCS from Ohio Sate and bleeds scarlet and gray.

Wilson Snyder, Developer of “Verilator”

Verilator: Fast, Free, But For Me? - pdf

  • Wilson Snyder is a consulting engineer with Cavium Networks in Marlboro, Massachusetts, USA.
  • A graduate of Rensselaer, he has worked at Digital Semiconductor and SiCortex, performing ASIC design and microprocessor architecture, and Maker Communications, and Sun Microsystems, where he designed network processing chips.
  • He makes regular and numerous contributions to public domain engineering tools, such as Verilog-Mode for Emacs and Verilator, available off his Veripool.com web site.

Chad Spackman, Verification Technologist

Verilator: Fast, Free, But For Me? - pdf

  • Chad Spackman, founder and CTO of two ESL based IP companies, has 20 years of semiconductor design experience and holds five patents in the field.
  • Chad's achievements include over a dozen analog designs for various foundries, six large-scale communications ASIC designs in the communications sector, and a complete TCP/IP TOE engine licensed to a major semiconductor company.
  • Chad holds a BA in physics and Bachelor and Master's degrees in Electrical Engineering from the University of Pennsylvania and Penn State University, respectively.

Michael Theobald - D.E. Shaw Research

  • Michael Theobald designs practical formal verification methods for complex circuits at D.E. Shaw Research.
  • He is involved in the development of a special-purpose machine for molecular dynamics, called Anton.
  • Michael also teaches as an Adjunct Professor in the Computer Science Department at Columbia University.
  • Michael received a Ph.D. from Columbia University in 2002 and a Diplom from Johann Wolfgang Goethe-Universitaet, Frankfurt, both in computer science.
  • Prior to joining D.E. Shaw Research in 2004, he was a Postdoctoral Fellow in the Computer Science Department at Carnegie Mellon University with Edmund Clarke.

Swaminathan Venkatesan - Cadence, Bangalore

HW-SW Co-Verification : A Constrained Random Approach - pdf

  • Swaminathan Venkatesan has over 10 years of experience in Design and Verification of complex network asic’s, processors and SoC
  • He is currently working at Cadence Design Systems, Bangalore as a Technical lead for Incisive Verification Kit
  • Swaminathan's interests include SoC Verification Methdologies, System Low Power verification and Metric driven Acceleration
  • Swami has presented verification seminars and workshop at various conferences organized by IPSoC, VLSI Society of India and at CDNLive!
  • Swami holds a Masters Degree from Indian Institute of Science and a Bachelors from Madras University