Brian Bailey - Functional Verification & ESL Expert

Is it Time to Declare a Verification War? - pdf

  • Brian currently stays busy as a reviewer, technical program member and track chair for a number of conferences, including DATE and DAC as well as serving on the Technical Advisory Board for Jasper Design Automation.
  • Brian currently serves as chair of the Accellera Interfaces Technical Committee, which has successfully developed a co-emulation standard that is now getting widespread adoption in the market.
  • In 2007, Brian published, along with Grant Martin and Andrew Piziali, what is becoming the definitive work on the Electronic System Level (ESL) Design and Verification space.
  • He has also authored two books: The functional verification of digital systems, and Taxonomy for the development and verification of electronic systems
  • Brian's work has resulted in four patents issued with others currently pending.
  • As a point of note, Brian also worked as engineering and project manager on HILO, the worlds first commercial RTL simulator at Brunel University in London – 1987.

Andrew Bond - Icera Inc.

Practical Implications of Adopting OVM/SV - pdf

  • Since 2004, Andrew Bond has been a member of the silicon design/verification and software driver teams at Icera Inc, which designs chipsets for mobile broadband devices.
  • Andrew is currently responsible for organizing the effort behind Icera's non-formal approach to functional verification.
  • Beforejoining Icera, Andrew workedon the SH4/ST40 and SH5/ST50 projects as a part of both ST and SuperH Inc. as a verification engineer.
  • Andrew holds a Masters Degree in Theoretical Physics from the University of Exeter.

Chris Brown - Texas Instruments UK

Progressive Migration from 'e' to SystemVerilog: A Case Study - pdf

  • Chris has been with Texas Instruments UK since 1997. During this time he has lead a wide variety of IC verification projects.
  • Chris has architectured testbenches for TI using both VHDL, E and SVTB and has verified complex SOCs, small digital IPs and large complex mixed signal designs.
  • Chris holds a PhD/BEng from the University of Sheffield and is a Member of Group Technical Staff at TI.

Matthew D. Clark, Northrop - Grumman IT (TASC)

Validation and Design in a Small Team Environment - pdf

  • Matthew Clark is a Communications Systems Engineer at Northrop Grumman - Information Systems, and has previously been employed as an ASIC/FPGA designer and team lead at Intel, Nortel, and Raytheon.
  • His research interests cover all areas of implementing analog and digital signal processing functions in digital hardware.
  • Matthew earned a Ph.D in ECE, an MSEE, and B.Computer Engineering from the Georgia Institute of Technology, as well as a B.S. from St. Andrews Presbyterian College

Kersten Eder, Professor - University of Bristol

Formal Verification - Academic Research in the UK - pdf

  • Kersten teaches and performs research related to functional verification at the University of Bristol, the leading European university in Advanced Verification Methodology.
  • Much of her work is responsible for leading the Cadence Academic Network.
  • She is currently engaged in research projects at MSc and PhD/EngD level with the local industry.
  • Some of these projects are currently focused on coverage-directed stimulus generation.

Sakar Jain, Networking and Multimedia Group - Freescale Semiconductor

Formal Verification of the Verification of the QorIQ Communication Platform’s CoreNet Fabric with SystemVerilog - pdf

  • Sakar Jain is a Senior Verification Engineer in Networking and Multimedia Group (NMG) at Freescale Semiconductor, Austin Texas.
  • He has many years of progressive experience in using advanced verification methodologies for design verification of microprocessors and SoCs.
  • He is currently working on QorIQ line of communication processors from Freescale.
  • Prior to joining Freescale, Sakar worked at IBM, Austin and was a key member of Cell microprocessor design team.

Chris Kappler - Achilles Test Systems

Insights and Lessons Learned Verifying the QoS Engine of an Innovative Network Processor - pdf

  • Christopher Kappler is CEO at Achilles Test Systems, which provides consulting services and products that maximize the value of customer tools and methodologies by summarizing tool and simulation outputs in collaborative dashboards.
  • Prior to Achilles Test Systems, Christopher worked at Cisco Systems and was the lead architect of the QoS Engine used in Cisco's Quantum Flow Processor. He was instrumental in its conception, architecture, development and successful release.
  • Prior to that, Christopher lead an architectural group at Hammerhead Networks which was acquired by Cisco in 2002.
  • Since 1992, he has worked on ASIC, EDA, and embedded software projects at companies such as C-Port, Meta Systems, Mitsubishi, UB Networks and Sun Labs.
  • Christopher has a Ph.D. from Syracuse University in Computer Systems Engineering, where he was a GAANN Fellow. His MS and BS degrees are also from Syracuse.

Narasimha Karunakar - AMD Bangalore

Low Power Verification Challenges - pdf

  • Narasimha Karunakar is currently working as a Senior Design Engineer at AMD Bangalore and responsible for setting up the flow and driving the methodology for Power Aware Simulations for complicated Microprocessors.
  • Narasimha has been working in ASIC design and verification since 2000.
  • His expertise is mainly in the areas of functional verification by using state of the art verification techniques using Specman and VERA for complex ASICs. Narasimha was involved in development of complex test benches & verification of modules in Network chips and storage devices.
  • Narasimha has also worked on Design, Synthesis, and Timing Analysis as part of ASIC Design flows. Narasimha has won several “Best Performer” awards for his outstanding and consistent performance.

Jai Kumar - Sun Microsystems

Leveraging Low Cost FPGA Prototyping for Validation of a Highly Threaded Server-on-Chip - pdf

  • Jai Kumar is a Verification Technologist at Sun Microsystems. Jai spearheads evaluation and deployment of state-of-art verification technologies and methodologies to enhance verification efficiency of UltraSPARC Server-On-Chips.
  • Jai has more than 18 years of experience in microprocessor design and verification including UltraSPARC T2, T1, Fujitsu SPARC and Motorola ColdFire processors.
  • Jai also plays active role in the industry, chaired conferences and has 60+ publications and awards in the areas of simulation, emulation and formal verification to his credit. He has contributed the Verification Methodology chapter to OpenSPARC Internals Book.
  • Jai holds a MS in Computer Engineering from Syracuse University.

Sunil Kumar - Intel Bangalore

Trends in Mixed Signal Validation - pdf

  • Sunil Kumar is leading Mixed Signal Validation (MSV) of next generation microprocessor at Intel, Bangalore.
  • Sunil has been involved in defining MSV methodology in multiple projects.
  • Before MSV, he contributed in design and validation of 10Gb Ethernet Switch ASIC.
  • Sunil started his career in 1996 from C-DOT where he was involved in the design of two generations of ATM Switching systems.
  • Sunil has a BE from MNNIT, Allahabad and a MSc (Eng.) from IISc, Bangalore.

Shahram Salamian, Ultra Mobility Group - Intel

Intel Atom Processor Pre-Silicon Verification Experience - pdf

  • Shahram Salamian has been with Intel for the past 12 years where has worked on CPUs as well as Chipset & GFx products.
  • For the past 5 years, Mr. Salamian has managed an Austin group in charge of pre-silicon verification for Intel lower power CPUs and SoC products.
  • Prior to Intel, he was at IBM for 10 years in the design & verification division for CPUs and chipsets.
  • Mr. Salamian holds an MSEE from University of Minnesota.

Doug Smith - Doulos

How to Handle Asynchronious Behaviors Using SVA - pdf

  • Doug is a verification specialist for the world-class training and consulting company Doulos. He regularly delivers training in the industry standards such as SystemVerilog, Verilog, VHDL, and industry recognized verification methodologies like OVM and VMM.
  • Prior to Doulos, Doug led and managed a team of consulting verification engineers in Eastern Europe offering SoC and IP verification services on large-scale designs such as Texas Instrument’s OMAP processors and Freescale's GSM radio. His team also focused on 802.11 MAC and PHY verification and specialized in synthesizable, emulation-friendly verification IP.
  • Prior to working overseas, Doug worked at Sun Microsystems for many years performing block and fullchip verification as part of the UltraSparc microprocessor team and the Workgroup Server ASIC emulation team.
  • Doug holds a masters degree in Computer Engineering from the University of Cincinnati and a bachelors degree in Physics and Biology from Northern Kentucky University. Currently, he resides in Austin, Texas.

Sean Smith - Juniper Networks

Design Verification: The Past, Present, and Future - pdf

  • Sean Smith is currently a verification engineer at Juniper Networks. Previously at Denali Software, Mr. Smith has acted as chief verification architect and director of field applications.
  • Prior to his role at Denali Software, Mr. Smith was a verification engineer at Cisco Systems, where he led verification efforts on numerous systems, application specific integrated circuits (ASICs) and system-on-chips (SoCs) using a wide variety of verification techniques and technologies.
  • These included directed random testing, assertion-based verification, and coverage-based verification.
  • Mr. Smith is also an active contributor in industry-standards bodies including The SPIRIT Consortium, IEEE ,and Accellera. Mr. Smith received a Bachelor of Science in Computer Engineering from LSU.

Durgam Vahia - Sun Microsystems

Mapping Server-Class Multi-Threaded OpenSPARC T1 Processor Core on FPGAs - pdf

  • Durgam is leading OpenSPARC Engineering and Partnership Development at Sun Microsystems.
  • In his prior roles, Durgam has led and contributed in various projects in the areas of VLSI CAD tools development, logic design and microprocessor verification.
  • Durgam has keen interest in enabling multi core research throughout the world, by providing out-of-the-box and reconfigurable open-source hardware platforms; and believes OpenSPARC is key in making that happen.
  • Durgam received his MS in Computer Engineering from University of Massachusetts at Amherst and was a co-recipient of Sun's Chairman's Award for Innovation in 2004 for his work on the verification of memory consistency models.