Eric Aardoom, TD-SCDMA DV Lead - MediaTek Wireless, Inc.

Constrained-Random Thoughts on Design and Verification of Advanced DSP Blocks for Next-Generation Handsets - pdf

  • For the past 7 years, Eric was with the RF & Wireless Systems group at Analog Devices, Inc., where he was involved in the design and verification of baseband processor SoCs for GSM/GPRS, EDGE, and 3G handsets, first as design engineer and most recently as lead verification engineer.
  • Prior to crossing the Atlantic in 2000, he was research engineer in the VSDM division of IMEC vzw, Leuven, Belgium, research fellow at the University of Leeds, Leeds, UK, and research assistant at Delft University of Technology, Delft, the Netherlands.
  • In this past life, he worked on a variety of wireless and embedded system R&D projects, including space-based GPS/Glonass receivers for climate monitoring, a CDMA modem for a satellite-based store-and-forward network, and a software-defined multi-standard navigation system based on the MOVE configurable VLIW processor architecture.
  • Eric earned his MScEE degree from Delft University of Technology in the Netherlands.

Willie Anderson, Vice President, Engineering for CDMA Technologies - Qualcomm

Evolving Wireless Markets & The Software Challenge, or Software Is The Answer, But What Is The Question? - pdf

  • Willie brings QCT over 19 years of experience in the semiconductor development and network engineering, including senior positions at Analog Devices, Motorola, and in private fabless semiconductor companies.
  • Willie was director of DSP development for Analog Devices' joint development with Intel. There, he managed a multi-discipline engineering team developing the Blackfin DSP core and associated tools for 3G Cellular, multimedia, and general purpose applications.
  • He also managed development of several products based on Blackfin at Analog Devices' Austin Design Center, and directed the development of the Blackfin DSP architecture from its beginning.
  • While at Motorola, Willie helped design arithmetic units, simulators, and application software for Motorola's 88K and PowerPC RISC processors. He also developed the architecture for and managed the development of advanced DSP processors for communication infrastructure applications.
  • Willie holds numerous patents in arithmetic unit, processor, system, and software design.
  • He received a bachelor's degree in physics from The University of Texas at Austin where he also did post-graduate work in high-energy plasma physics.

Jais Abraham - AMD Design Centre Bangalore

Nanometer Testing: Challenges and Soultions - ppt

  • Jais Abraham graduated from the Indian Institute of Technology at Chennai, India.
  • He has over 10 years of experience in the area of VLSI Design-For-Test, working at Texas Instruments (India), InnoDes Solutions and Montalvo Systems.
  • Currently, he is a Member of Technical Staff at the AMD India Design Centre, Bangalore.
  • During the span of his career, he has been involved in defining the DFT features of complex designs ranging from high speed processors to multi-million gate SOCs on cutting edge technologies.
  • He has co-authored several papers in National and International conferences and holds 6 patents in the area of DFT.

Brian Bailey - Functional Verification and ESL Expert

Is it Time to Declare a Verification War? - pdf

  • Brian currently stays busy as a reviewer, technical program member and track chair for a number of conferences, including DATE and DAC as well as serving on the Technical Advisory Board for Jasper Design Automation.
  • Brian serves as chair of the Accellera Interfaces Technical Committee, which has successfully developed a co-emulation standard that is now getting widespread adoption in the market.
  • In 2007, Brian published, along with Grant Martin and Andrew Piziali, what is becoming the definitive work on the Electronic System Level (ESL) Design and Verification space.
  • He has also authored two books:The functional verification of digital systems, and Taxonomy for the development and verification of electronic systems.
  • Brian's work has resulted in four patents issued with others currently pending.
  • As a point of note, Brian also worked as engineering and project manager on HILO, the worlds first commercial RTL simulator at Brunel University in London – 1987.

Mike Benjamin, IP Verification Manager - ST-NXP Wireless

Deploying Functional Qualification at STMicroelectronics - pdf

  • Mike has been actively involved in functional verification and dependable computing for more than 20 years.
  • Previously he spent eight years leading the central Functional Verification Group for STMicroelectronics. In that role he was responsible for driving the development and deployment of leading edge functional verification tools and methodologies.

Henry Chang, Co-Founder - Designers' Guide Consulting

  • Henry is an expert in analog/mixed-signal/RF design and verification methodologies, next generation tools and flows, and standards for analog & mixed-signal IP in system-on-a-chip design.
  • During his career he has designed and implemented several analog integrated circuits, written EDA software, developed system-on-a-chip design methodologies, and spent extensive time working with designers to understand their needs both short and long term and to provide solutions.
  • Henry co-founded Designer's Guide Consulting in 2005. From 1995 to 2005, Henry worked at Cadence Design Systems, Inc. in research and development, methodology services, product marketing, corporate strategy, and in the office of the Chief Technology Officer. He has also worked at Micro Linear and GE Lighting.
  • He is the author of three books: Winning the SoC Revolution: Experiences in Real Design in 2003, Surviving the SoC Revolution: A Guide to Platform Based Design in 1999, and A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits in 1997.
  • He is on the steering committee of the IEEE Custom Integrated Circuits Conference.
  • He holds 10 US patents, has authored 14 technical papers, and has participated at conferences giving tutorials, sitting on panels, and giving keynote addresses.
  • Henry received his Ph.D. and M.S. in Electrical Engineering from the University of California at Berkeley in 1994 and 1992 respectively.
  • He received his Sc.B. degree in Electrical Engineering from Brown University in 1989.

Tony Correale, Chief Engineer & Consultant - VLSI Engineering

Amorphous Voltage Islands: Integrated Approach to Lower AC & DC Power - pdf

  • Tony has worked as the IBM principal engineer for design engagements with Xilinx, AMCC, Cirrus/MiCRUS, UMC, Toshiba and Motorola.
  • Previously, he served as chief engineer & manager of the development team responsible for extending the 440 class embedded processors.
  • He has authored several technical papers in IEEE conferences, the IBM Journal of Research and Development, and the IBM Austin Conference on Energy Efficient Design. 
  • Tony also co-authored several IBM internal documents including the much acclaimed, VLSI Cost Management Development Guide.
  • Tony recently co-led an IBM Academy of technology study on VLSI design transformation.

David Dill, Professor of Computer Science - Stanford University

Dealing with the Three Horrible Problems in Verification - pdf

  • David L. Dill is a Professor of Computer Science and, by courtesy, Electrical Engineering at Stanford University. He has been on the faculty at Stanford since 1987.
  • He has an S.B. in Electrical Engineering and Computer Science from Massachusetts Institute of Technology (1979), and an M.S and Ph.D. from Carnegie-Mellon University (1982 and 1987).
  • Prof. Dill has research interests in a variety of areas, including computational systems biology and the theory and application of formal verification techniques to system designs, including hardware, protocols, and software.
  • He has also done research in asynchronous circuit verification and synthesis, and in verification methods for hard real-time systems.
  • He was the Chair of the Computer-Aided Verification Conference held at Stanford University in 1994.
  • From July 1995 to September 1996, he was Chief Scientist at 0-In Design Automation.
  • Prof. Dill's Ph.D. thesis, "Trace Theory for Automatic Hierarchical Verification of Speed Independent Circuits" was named as a Distinguished Dissertation by the Association for Computing Machinery (ACM), and published as such by M.I.T. Press in 1988.
  • He was the recipient of an Presidential Young Investigator award from the National Science Foundation in 1988, and a Young Investigator award from the Office of Naval Research in 1991.
  • He has received Best Paper awards at International Conference on Computer Design in 1991 and the Design Automation Conference in 1993 and 1998.
  • He was named a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2001 for his contributions to verification of circuits and systems, and a Fellow of the ACM in 2005 for contributions to system verification and for leadership in the development of verifiable voting systems.
  • Prof. Dill has been working actively on policy issues in voting technology since 2003. He is the author of the Verified Voting Foundation and and is on the board of those organizations. In 2004, he received the Electronic Frontier Foundation's "Pioneer Award" for "for spearheading and nurturing the popular movement for integrity and transparency in modern elections."

Kersten Eder, Professor - University of Bristol

Design Verification Research and Teaching - pdf

Formal Verification: Academic Research in the UK - pdf

  • Kirsten teaches and performs research related to functional verification at the University of Bristol, the leading European university in Advanced Verification Methodology.
  • Much of her work is responsible for leading the Cadence Academic Network.
  • She is currently engaged in research projects at MSc and PhD/EngD level with the local industry.
  • Some of these projects are currently focused on coverage-directed stimulus generation.

Darren Galpin, Design Verification Engineer - Infineon Technologies

Applying Apsect-Extended UML Modelling to e - pdf

  • Daren has worked in Product Engineering and Verification at STMicroelectronics, and in Verification at Infineon Technologies since 2000.
  • He is currently Module IP Verification Team Lead in Bristol

Gary Greenstein, Graphics Products Group - AMD

Verification of Graphics ASICs Part I , Part II

  • Gary is a verification architect and lead in the AMD Graphics Products Group, formerly ATI, in Marlboro MA.
  • Gary has held various technical and leadership positions at Sun Microsystems, Infiniswitch, Zaiq Technologies, and Synopsys.
  • He has a BS in Engineering from Princeton University, and a MS from the University of Illinois, Urbana-Champaign.

John M. Ludden - IBM

SMT Verification of the POWER5 and POWER6 High Performance processors - pdf

  • John Ludden is a senior technical staff member at IBM where he has over 18 years of experience in design verification spanning mainframes, x86 and PowerPC processor based systems.
  • He has been the architecture verification lead engineer for IBM's POWER3/4/5/6 processors and is a member of IBM's Verification Advisory Team.
  • For the past 14 years, John has worked with IBM's test generation research team in Haifa, Israel to improve instruction-level test generation capabilities in order to address out-of-order execution, symmetric multi-processing and simultaneous multi-threading (SMT) processor verification requirements.
  • John received a Corporate Award from IBM for his leadership in defining and executing the POWER5 SMT verification plan.
  • He has co-authored three papers and currently holds two patents in microprocessor verification.
  • John received his BSEE from the Rochester Institute of Technology in Rochester, New York in 1990.

Nilesh Ranpura, Project Manager ASIC Division - EInfochips

Modeling System Behaviors: A Better Design on Prototyping - ppt

  • Nilesh Ranpura has 10+ years of experience in VLSI Design Cycle, Methodology and Verification in the areas of Bus Interfaces and Networking devices.
  • He has participated on various projects for Verification IP architecture definition and Complete Product development.

Rowland Reed, Manager, Hardware Verification Team - Qualcomm Austin

Evolving Wireless Markets & The Software Challenge, or Software Is The Answer, But What Is The Question? - pdf

  • Rowland Reed manages the hardware verification team at Qualcomm-Austin. He joined Qualcomm in May 2007.
  • Rowland has more than 20 years experience in hardware and software defelopment, having worked in verification, verification tools development, and software development positions at Texas Instruments, IBM (Somerset Design Center), Tivoli, BOPS, Motorola/Freescale, Sigmatel, and now Qualcomm.
  • Rowland has a BSEE from Louisiana Tech and has done post-graduate work in computer science at The University of Texas.

Pradip Thaker - Analog Devices, Inc. Bangalore

Verification Strategy for PCI Express - ppt

  • Dr. Pradip Thaker has 15 years of industry experience combined both as a technical manager and as an individual contributor in developing large and complex ICs for networking, multi-media and computer connectivity with semiconductor and system companies in USA and India.
  • He also served as an adjunct faculty at the George Washington University (Washington DC, USA) from years 1993-2003 where he designed and taught undergraduate and graduate level VLSI courses on part-time basis.
  • He received BE (ECE), MS (EE) and PhD (VLSI Systems) in 1989, 1993 and 2000 respectively.
  • He is currently with DSP IC Division of Analog Devices, Inc. in Bangalore, India.
  • Dr. Pradip Thaker is the recipient of industry and academic awards for excellence.
  • He has published in international conferences and regularly reviews papers for the same.
  • His technical contributions in industry are in the areas of architecture definition, RTL implementation, verification, synthesis and DFT. His academic research interests are in area of DFT and verification.

Steven Schulz -

Low Power Design Verification - pdf

  • Since 2002, Steve Schulz has served as president and CEO of Si2, the leading worldwide consortium of semiconductor and software companies chartered to develop EDA standards.
  • Steve was previously VP of corporate marketing for BOPS Inc. and was employed by Texas Instruments for 19 years.
  • At TI, Steve was a Senior Member of the Technical Staff and held a wide variety of management and technical positions, including CAD strategy manager and reliability strategy manager.
  • Representing TI, he served as chairman of the Design Sciences Technical Advisory Board for Semiconductor Research Corporation.
  • Steve has vast experience in standards, having served as president of VHDL International, co-chairman of Accellera, and chairman of the VITAL and SLDL/Rosetta standards initiatives.
  • He has authored more than 150 articles on EDA and IC design methodology, and was a founding editor of Integrated Systems Design magazine.
  • Steve has served on numerous Boards, including CADstone Inc.,, ProphICy Semiconductor, and CMP Publications.
  • Steve has a Bachelor of Science degree in electrical engineering from the University of Maryland at College Park, and an M.B.A. from the University of Texas at Dallas.
  • He is an active jazz trombone musician in the Austin area.

Praveen Vishakantaiah, President - Intel India

Validating Next Generation CPUs - ppt

  • Praveen Vishakantaiah is currently the Intel India President and also the Director of Digital Enterprise Group in India. He is responsible for all the Intel activities in India.
  • Praveen joined Intel in 1993 and managed the development and deployment of software based fault simulator for Pentium® Pro microprocessor.
  • He was one of the winners of the first Intel Innovators award in 1995.
  • Starting 1996, he was part of the microprocessor design team for more than 7 years contributing to the development of Pentium® II, Pentium® III and Pentium® 4 microprocessors by first managing various aspects of design for test technology and later being the design automation manager.
  • He relocated to India in 2003 to start the Processor System Validation group with focus on post-silicon validation and enabling of ingredients for Xeon® server platforms.
  • Praveen holds MS and Ph.D degrees in Electrical and Computer Engineering from The University of Texas at Austin.
  • He obtained his Bachelor of Engineering degree with Honors in Electronics and Communication from Regional Engineering College, Tiruchirapalli, India.

David Whipp, Verification Architect - NVIDIA

Stop Writing Assertions! Creating Efficient Verification Methodologies pdf

  • Dave has spent 15 years doing verification and modeling since graduating from UMIST in 1993.
  • He began his career working on an early SoC methodology at one of the first ARM licensees; since then he has worked on verification of DSPs, microcontrollers and network processors at various companies.
  • For the past 5 years he has worked as a Verification Architect at NVIDIA, focusing on unit level simulation environments and transaction level modeling with assertions.
  • David also works as Track Chair for the Functional Verification track at DesignCon.

Shaw Yang, Graphics Products Group - AMD

Verification of Graphics ASICs  Part I , Part II

  • Shaw is a Senior ASIC Manager in the AMD Graphics Products Group, formerly ATI, in Marlboro MA. Shaw is responsible for the verification of Graphics ASICs.
  • From 2005-2007, Shaw was the VP of Business Development at Avery Design Systems focusing on verification IPs.
  • From 1994 to 2004, Shaw worked at SUN MicroSystems Enterprise Server Engineering where he the Director of ASICs Engineering responsible for the development of all of SUN's Enterprise Server ASICs.
  • From 1986-1994, Shaw was an ASICs engineer and manager at Thinking Machines Corp in Cambridge MA. He was a key contributor to the development of the CM-2 and CM-5 massively parallel supercomputers.
  • In the early 1980's, Shaw worked in HP Integrated Circuits Division in Cupertino CA.
  • Shaw has a BS EECS from Princeton University and a Masters of Engineering from Cornell University.