Unmesh Agarwala - Juniper Networks

  • Unmesh Agarwala is presently VP of Hardware Engineering for the Infrastructure Products Group at Juniper Networks where he manages a global dispersed team of engineers.
  • He has 25 years of industry experience and has previously held management and engineering positions at SGI, Tandem Computers and Intel.
  • Unmesh holds a B.S.E.E. from the Indian Institute of Technology in Mumbai and a M.S.C.E. from the University of Southern California in Los Angeles.

Bob Fredieu - EE Consultant

Does Design Verification Have a Future? - pdf

  • Bob is an independent verification consultant in the Boston area.
  • He has been consulting since the late '80s in design, verification, architecture, and project management.
  • His customers include many local companies as well as in other eastern states, California, Texas, and Europe.
  • Bob holds an S.B. in EE and an S.B. in Physics from MIT.

Sanjay Gupta - IBM

Cell Verification Metrics - pdf

  • IBM, DV Manager, STI

Scott Herrington - Zilker Labs

Zilker Labs Mixed-Signal Verification - pdf

  • Scott has more than 20 years of experience in IC design and engineering management.
  • Most recently Scott was Vice President of Engineering at two semiconductor startups, Server Engines and LayerN Networks.
  • His work experience also includes ESS Technology, Crystal Semiconductor/Cirrus Logic, Ross Technology, Lattice Semiconductor and Texas Instruments.
  • Scott holds a Masters degree in Electrical Engineering from Southern Methodist University and has authored numerous patents.

David John Lacey - Hewlett Packard

What's with all this talk about coverage? - pdf

  • David has been with HP for five years after nearly ten years with Raytheon.
  • He has primarily focused on system verification of chipsets used in HP’s high end servers.
  • David has also been involve in industry standardization activities and has held roles within Accellera as chairman of the OVL technical committee and member of the SystemVerilog Assertions technical committee.
  • As co-author of Assertion-Based Design, David has pioneered assertion use and methodologies. He has three patents in verification awaiting approval with the US Patent office.

Jim Lear - Legerity

Reuse and Collaboration Opportunities in AMS Design and Verification - pdf

  • Jim Lear, in addition to his digital design duties, has lead the development of the mixed-signal verification methodologies for the past seven years at Legerity, Inc.
  • He has developed easy to use dynamic frequency domain modeling techniques for discrete-time simulations, modular signal-analysis testbenches, and modeling techniques for discrete-analog devices (e.g. resistors and capacitors) and I/O impedances in logic-simulators.
  • He has authored and co-authored several papers on mixed-signal verification, including a DesignCon Best Paper, and DesignCon East Best Paper Finalist in functional verification.
  • Prior to Legerity, Jim was a digital designer for DEC, Centaur Technology, and Motorola.

Mayur Mehta

D2Audio Verification Flow - pdf

  • Mayur Mehta has over 15 years of Design and Verification experience covering microprocessors, ASICs, Digital Audio, Board Design, and Embedded Software.
  • He has held leadership positions at Ross Technologies, Equator Technologies, OmegaBand, and Sierra Logic. In early 2005 he was recruited back to Austin to lead the engineering effort at D2Audio.

Shrenik Mehta - Sun Microsystems

OpenSPARC T1 Processor - pdf

  • Shrenik Mehta is the Director of Frontend Technologies and OpenSPARC program.
  • As Director for Frontend Technologies he is responsible for the tools and methodology in the areas of Simulation/Hardware Acceleration, Formal Verification, Testability & Debug tools, Implementation and Verification IP used in the development and validation of A SICs, Processors and Systems.
  • As OpenSPARC Program Director, Shrenik has been driving the details from the infancy of the project to the public release of the deliverables and looks forward to building a larger OpenSPARC community. The OpenSPARC community contributors and partners can explore and innovate in Multi-threaded algorithms and applications, Operating Systems, System Architecture, EDATools/Methodology, Circuit implementations, Compiler Tools, System Modeling, System on a Chip, Debug tools, Performance analysis and benchmarking, Implementation and Verification IP.
  • Shrenik is currently the Chairman of Accellera, an industry standard's organization Accellera's mission is to drive worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. He was also the Vice-Chair of IEEE 1800 SystemVerilog Working Group.
  • During his 15+ years at Sun, Shrenik has been involved with SPARC and Java hardware designs. He managed verification of 5 SPARC processor products. the first single chip integration of the SPARC Integer Unit and Floating Point Unit called Mini, microSPARC-I, microSPARC-II, the first 64 bit UltraSPARC I and UltraSPARC IIi. Prior to Sun, Shrenik had worked as a Design Manager at Nexgen Microsystems working on X86 compatible processor. Prior to Nexgen, Shrenik worked as a designer on graphics and FDDI Networking products at AMD.
  • He holds eight US Patents and one patent in Taiwan.
  • Shrenik enjoys the outdoor activities like hiking, skiing, running, camping. Currently spending his spare time learning piano.

Milind Padhye - Freescale Semiconductor

Wireless Low Power and Verification Challenges - pdf

  • Milind is a Low Power Design Manager in the Freescale Wireless group. He has been working on multiple low power initiatives at Freescale and has multiple patents and disclosures in low power design. Milind has worked closely with multiple EDA vendors to drive low power design methodologies.

Rob Porter - Hewlett Packard

What's with all this talk about coverage? - pdf

  • Rob has been with HP for nine years, and was previously at Texas Instruments for five.
  • He has spent the last 12 years in verification, both for processors and chipsets.
  • His interests are the practical application of coverage tools and assertions, methodologies for obtaining and managing design information critical to the verification process, and effective definition of verification activities.
  • Rob is co-inventor for a patent on a self-checking testplan execution environment.

Somdipta Roy, Design Verification Lead - Apple

OMAP Verification - pdf

  • Somdipta Roy has almost 20 years of design verification experience of complex processors (ARM family, TI DSP family), IPs, subsystem and SOCs (TI's OMAP class of devices).
  • Before working for apple, Somdipta has been employed by Qualcomm, Broadcom, and Texas Instruments

Subrata Roy, Senior Design Engineer - Silicon Labs

Verifying Power Domains in AeroFONE - pdf

  • Subrata Roy is a Senior Design Engineer in the Wireless Division of Silicon Laboratories.
  • Prior to joining Silicon Labs he was at Agere Systems, NJ working on verification of 3G Digital Baseband ICs and at AT&T/Lucent Bell Labs working on DFT methodologies.
  • He has a Bachelors in Electronic Eng. from I.I.T. -Kharagpur, a Master's in Computer Science from I.I.T-Kanpur followed by a 2 year stint at Rutger's University, NJ doing Graduate research on VLSI design methodologies.

Shahram Salamian - Intel

CPU Verification Metrics - pdf

  • Shahram has worked for 11 years at Intel on verification on CPUs, Graphics/Chipsets and recently SoC.
  • Currently he is an Ultra Mobility Group CPU pre-silicon verification manager.
  • He worked for 11 years at IBM, mostly in design and some verification on CPUs (System 38) and variety of cache & IO controller chipsets.

Mike Schuh - Foundation Capital

  • Mike has more than 35 years of experience in the software industry, including four technology start-ups. Twice in his career, Mike has created market-leading enterprise software companies: Computervision in the CAD/CAM market and Cadence in EDA (Electronic Design Automation). There are very few operational challenges Mike hasn't faced and tackled successfully somewhere along the line.
  • Before joining Foundation Capital in 1998, Mike was CEO, co-founder, and chairman of the board of Intrinsa Corporation, a software applications company that was acquired by Microsoft. Mike was the vice president of sales at Clarify, Cadence Design Systems and Computervision prior to co-founding Intrinsa.
  • Mike currently serves on the boards of Netflix (NFLX), Responsys, BoardVantage, ONStor, Jasper Design Automation and VaST.
  • Mike has been a passionate runner for more than 30 years, and has successfully completed 20 marathons. Mike has an affinity for California wines.
  • Mike received a BSEE from the University of Maryland.

Ravi Selvaraj, SiNett Corp.

  • Ravi has over 15 years of experience in ASIC/chip development and engineering management.
  • He was the first ASIC engineer hired at Maverick Networks and was a key member responsible for the now famous StrataSwitch product line.
  • He has successfully designed and delivered multiple complex high-density 0.13u silicon.
  • He is recognized as an industry leader in deep sub-micron design.
  • Ravi has extensive knowledge in front-end and back-end chip development, and high-speed networking design.
  • Ravi holds an MSEE and has finished 3-year course work towards a PhD at RPI.

Aaron Shreeve - Zilker Labs

  • Aaron Shreeve is an analog IC designer for Zilker Labs.
  • He was previously employed at AMI Semiconductor.
  • Aaron has his MSEE and BSEE degrees from Brigham Young University.

Jason Stinson, Enterprise Microprocessor Group - Intel

Pre-Si Verification for Post-Si Validation - pdf

  • Jason is a principal engineer in the Enterprise Processor Division at Intel Corporation. He received his B.S. and M.S. degrees in electrical engineering from Stanford University in 1990 and 1991, respectively.
  • In 1992, he joined Intel Corporation in the Microprocessor Design Division, working on the design of the original Pentium® Processor. For the past twelve years, Jason has been part of various microprocessor design projects at Intel, including the Pentium II Processor, Mobile Pentium II Processor and Celeron® Processor. During this timeframe, he has split his time between design methodology and post-silicon validation.
  • In the area of design and design methodology, Jason has been responsible for dynamic circuits, clocking, signal integrity and timing analysis on various projects.
  • In the area of post-silicon validation, Jason’s expertise areas are primarily in marginality validation and frequency debug.
  • For the past four years, Jason has been the circuit technical lead for the 0.13um Itanium® 2 Processor, responsible for both the global design methodologies as well as post-silicon validation.
  • Jason has authored 10 papers in refereed conference and technical journals. He has been awarded 3 US patents. Additionally, Jason has taught classes in advanced digital design at Stanford University and post-silicon validation at international conferences.

Paul Tobin, Director, Verification COE - AMD

Verification in a Global Design Community - pdf

  • Paul Tobin is Director of AMD's Verification Center of Expertise.
  • His worldwide team is responsible for improving the productivity of AMD's functional verification teams via consolidation of existing methods and introduction of new techniques.
  • Mr. Tobin joined AMD in July 2004 with responsibility for the management and technical direction of the Microprocessor Design Verification team at AMD's Boston Design Center.
  • Prior to joining AMD, he held positions as a verification architect for Sun's UltraSPARC V processor, director of system software at network processor vendor SiTera (acquired by Vitesse), and a microprocessor design engineer and manager at Hewlett Packard.
  • Mr. Tobin holds a B.S.E.E. from the University of Notre Dame and M.S.E.E. from the University of Illinois, Champaign.

David Williamson, Verification Manager - ARM

Verification Metrics - pdf

  • David is a Verification Manager for ARM

Brian Wong - D2 Audio

Digital Media Drives IC Content - pdf

  • Mr. Wong joined D2Audio as President and CEO in February 2005 and has over 23 years experience in executive and general management, marketing, and the development of mixed signal products and semiconductors.
  • Mr. Wong comes to D2Audio from Primarion, a leading mixed signal semiconductor company focused on digital control of power and optical I/O.
  • During almost 5 years at Primarion, Mr. Wong held roles as Interim CEO, EVP Marketing/Bus Dev, VP Engineering, and General Manager.
  • Mr. Wong was responsible for the marketing and business strategy to enable Primarion's growth from a startup company into a market leading mixed signal IC company based on their innovative power and I/O technology and products.
  • Prior to Primarion, Mr. Wong served for 17 years at TRW, where he was manager of the Mixed Signal Products business. At TRW, he was responsible for the development, manufacturing, and marketing of high performance data converters and digital transceivers.
  • Prior to TRW he worked at Xerox Microelectronics Center, where he developed MOS digital circuits.
  • Mr. Wong has co-authored a textbook and numerous papers on mixed signal and communication technology.
  • He holds a BSEE from University of California, Los Angeles, a MSEE from University of Southern California, has taken graduate management classes at UCLA Anderson School of Management, and serves on the Board of Advisors for the University of California, Davis Electrical and Computer Engineering Department.

Paul Zehr - Intel

Intex Xeon Pre-Silicon Validation - pdf

  • Paul is currently a Xeon processor pre-silicon validation technical lead.
  • Previously, he led various pre-silicon and post-silicon functional validation efforts on many IPF projects, including the first IPF processor, Merced.
  • Paul developed pre-silicon cluster test environments, including the first cache-MP cluster environment capable of using either real chipset RTL, or an emulated chipset model.
  • As a technical leader, he was responsible for the micro-architectural full chip checker.
  • In post silicon, he has developed several test generators focusing on both functional verification as well as circuit marginality testing. The post silicon MP test generation tool developed for IPF processors has been ported for use on ia32 processors in order to stress certain aspects of the design.
  • Paul initiated and led test content generation forums, focusing on improving post silicon test coverage utilizing a wide variety of test generation techniques for functional correctness.
  • Paul joined Intel in January of 1996, has one patent, and has authored 5 papers. Before joining Intel, Paul spent nine years in the IBM mainframe division as a design and validation engineer. His accomplishments there include team leadership of TBS switch chip validation and mainframe cache validation.
  • He was responsible for the design of four bipolar chips in the ES9000 cache, and designed the 121-chip cache TCM (Thermo-Cooled Module) on the ES9000.