As summer winds down and football season starts up, it's time once again for another DVClub lunch. As always, this is a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Come catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible.

This time around we have a double-feature from our friends at ARM, who have been extremely busy doing awesome things. First up we have Vikram Khosa presenting "Deep-Formal Deployment on an A-class ARM CPU Family : An Overview and Lessons Learned!" Next we have his colleague Vaibhav Agrawal speaking about "Two Case Studies in Formal Deployment on ARM CPUs: Instruction-Fetch and Floating Path Datapath"

This will be another awesome event, we look forward to seeing you there!

Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, Sep. 13, 2017 from 11:30 AM to 1:30 PM (CST)
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Agenda

11:30am Doors Open / Networking
12:00pm

Lunch and Feature Presentations

  • Vikram Khosa - "Deep-Formal Deployment on an A-class ARM CPU Family : An Overview and Lessons Learned!"
  • Vaibhav Agrawal - "Two Case Studies in Formal Deployment on ARM CPUs: Instruction-Fetch and Floating Path Datapath"
1:00 pm

Networking

Registration Now Open - Click to RSVP

Presentation One:

"Deep-Formal Deployment on an A-class ARM CPU Family : An Overview and Lessons Learned!" by Vikram Khosa, ARM

About Vikram Khosa:

Vikram Khosa currently leads the CPU formal verification effort at ARM's Austin design center. where he was previously memory-system verification lead for the Cortex-A15 CPU. Other experience includes CPU/ASIC/SoC verification roles with multiple companies, including 2 early-stage startups. He has a B.E. (Hons.) from BITS, Pilani and a Masters in Computer Engineering from University of Minnesota, Twin Cities

Presentation Two:

"Two Case Studies in Formal Deployment on ARM CPUs: Instruction-Fetch and Floating Path Datapath" by Vaibhav Agrawal, ARM

About Vaibhav Agrawal:

Vaibhav Agrawal is a Validation Engineer at ARM, where he applies formal techniques to verify “Instruction-Fetch” unit, and “Floating-point datapath” units in ARM’s locally designed A-class Cores. Prior to joining ARM, Vaibhav was a design automation engineer at Intel-Austin, where he worked on various aspects of RTL design and validation flows. He has a Masters in EE from UT-Austin, and a B.Tech in EE from Indian Institute of Technology, Delhi.