Please join us in Portland for this exciting DVClub event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.

For this event Cliff Cummings, president of Sunburst Design, will be presenting "SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage." Cliff has won many awards as a speaker atvarious past events and conferences. Not only is Cliff an experienced presenter who is always great to listen to, he has conducted many training classes around the world. You definitely won't want to miss this one.

We look forward to seeing you there!

Thursday, June 8 2017 from 11:30 AM to 1:30 PM

Portland Community College (PCC) Willow Creek Center
241 SW Edgeway Drive
Beaverton, OR 97006
View Map


11:30am Doors Open / Networking
12:00pm Lunch and Presentation
1:00pm-1:30pm Networking

Registration Now Open - Click to RSVP

Presentation by Cliff Cummings, President, Sunburst Design:

SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage  

SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. Best known practices suggest that it is better to add most assertions using bindfiles. This paper will explain why adding assertions directly to the RTL code can be problematic and why bindfiles solve many of the problems. This paper also explains how to use bindfiles efficiently and why engineers should generally use concurrent assertions while avoiding immediate assertions. This paper will also give assertion coding guidelines and styles that help reduce assertion coding effort, assertion coding mistakes and encourage designers to be more proactive in adding assertions to their designs.

Cliff Cummings

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training. Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted "BestPaper." Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.