Please join us for the next DVClub Silicon Valley event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.

For this event Eldon Nelson from Intel will be presenting "Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation." Eldon is fresh off of a second-place win for this presentation at DVCon this year, so you definitely don't want to miss this!

In addition to the lunchtime presentation, please stick around for an informative tutorial by Breker CEO Adnan Hamid. Adnan is an industry expert in portable stimulus, which was by far the hottest topic at the last DVCon.

We look forward to seeing you there!

Wednesday, May 24, 2017 from 11:30 AM to 1:50 PM

Dave and Buster's
940 Great Mall Drive
Milpitas, CA 95035
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11:30am Doors Open / Networking
12:00pm Lunch and Presentation by Eldon Nelson, Intel
1:00pm Tutorial by Breker Verification Systems

Registration Now Open - Click to RSVP 

 Keynote Presentation: "Improving Constrained Random Testing by Achieving Simulation Verification Goals through Objective Functions, Rewinding and Dynamic Seed Manipulation"

Constrained Random simulation is so critical to modern verification environments that it is a major component of the SystemVerilog language itself. This paper proposes a method that improves how UVM Constrained Random simulations are run. By abstracting the purpose of a simulation to be achieving “Objective Functions” (nominally coverage goals), it is possible to have the simulation autonomously explore deep possibilities from multiple points in time of a standard UVM testbench governed by feedback. This method has a number of benefits including: faster automated coverage closure, an efficient final stimulus solution and proposed higher quality of coverage.

About the Speaker: Eldon Nelson

Eldon Nelson is a Verification Engineer working at Intel. He received his B.S. and M.S. degree in Electrical Engineering from the University of Minnesota and is a licensed Professional Engineer (P.E.). Eldon's technical blog: features posts on verification and GNU Emacs - two of his favorite topics. He is an IEEE Senior Member and has had opportunities to serve as a volunteer in a variety of positions; and is presently the elected IEEE Twin Cities Vice-Chair. He has one US patent currently granted and four published papers in Verification. Before working at Intel, he has worked for: Micron Technology, IBM and the National Science Foundation.


Tutorial: "Portable Stimulus with Breker’s TrekSoC tool"

Adnan Hamid, CEO, Breker Verification Systems

Portable Stimulus is the next big thing in Functional Verification! In this tutorial we will look at creating self-checking models that capture verification intent. These models can be run under UVM at the unit level and sub-system level and using Software Driven Verification (C test cases) at the full chip level in simulation, emulation or post silicon. We will look at debug, coverage and coverage closure in each environment.

Adnan Hamid - Adnan has spent some 20 odd years researching how engineers reason about and represent verification knowledge, and developing strategies for automating test scenario generation from these representations. His prior roles include managing AMD’s system logic division, leading AMD’s microprocessor verification group and serving as subject matter expert in System Level Verification at Cadence. He received BS degrees in Electrical Engineering and Computer Science from Princeton University and an MBA from the University of Texas at Austin.