Please join us for the next DVClub Silicon Valley event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.

For this event Cliff Cummings from Sunburst Design will be presenting "SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage." Cliff is a well-known and entertaining speaker with numerous conference awards for his papers, you'll not want to miss it!

We will also feature two tutorials after lunch, one by Avery Design Systems entitled “Gate Simulation signoff throughout by handling the noise from False X’s,” presented by Andy Stein. The other tutorial will be "Next Generation Verification Planning and Management Solution Overview," from Cadence Design Systems, presented by Roxan Saint-Hilaire.

We look forward to seeing you there!

Wednesday, January 11, 2017 from 11:30 AM to 1:50 PM

Dave and Buster's
940 Great Mall Drive
Milpitas, CA 95035
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11:30am Doors Open / Networking
12:00pm Lunch and Presentation by Cliff Cummings, Sunburst Design


1:10pm Tutorials by Avery Design Systems and Cadence Design Systems

Registration Now Open - Click to RSVP 

 Keynote Presentation: "SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage"

SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. Best known practices suggest that it is better to add most assertions using bindfiles. This paper will explain why adding assertions directly to the RTL code can be problematic and why bindfiles solve many of the problems. This paper also explains how to use bindfiles efficiently and why engineers should generally use concurrent assertions while avoiding immediate assertions. This paper will also give assertion coding guidelines and styles that help reduce assertion coding effort, assertion coding mistakes and encourage designers to be more proactive in adding assertions to their designs.

About the Speaker: Cliff Cummings

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training. Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted "BestPaper." Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.


Tutorial: "Gate Simulation signoff throughout by handling the noise from False X’s"

Andy Stein, VP Sales, Avery Design Systems

Many companies that are using gate simulation to verify functionality already understand that, despite efforts to clean up potential “X” issues in RTL, their post-synthesis and optimization results can produce additional sources of “X” in their gate netlist. Some of the effects of the X's in gate simulation are not real, but are mainly artifacts of Verilog simulation being overly pessimistic. As design and verification engineers race against the clock to analyze the results in order to find real problems, the noise created by the false X’s can cause too much wasted time. As such, some companies have more brute force methods, such as initializing all flops to some artbitrary value and run multiple simulations to hope they have not masked a real issue. Avery Design System has had a product on the market for many years, SimXACT, to help companies take a more conservative approach to removing the noise from false X’s by applying the tool dynamically during simulation to remove those false X’s and using formal analysis to prove the correctness of the fixes.


Tutorial: "Next Generation Verification Planning and Management Solution Overview (vManagerTM)"

Roxan Saint-Hilaire, Applications Engineering Director, Cadence

Cadence vManagerTM Metric-Driven Signoff Platform, enabled by client server technology is the only second generation verification planning and management solution for pre-silicon functional verification. This enterprise class solution connects people and process’s for small to ultra-large verification projects, and from simple standalone test execution to large-scale database-enabled metric-driven verification (MDV) programs. With the vManagerTM platform, you benefit from optimal resource utilization, higher quality silicon, and a more predictable path to verification closure. The demonstration of vManagerTM will show all of the primary aspects of the tool, from creation of an executable verification plan to reporting of results. The vManagerTM process starts with a UVM or software test which is executed by a built in regression environment with a direct controllability to load sharing utilities on the farm. Tests can be driven by vMangerTM or collected from the users automation scripts. Test triage and coverage analysis is performed thru a powerful GUI based intuitive user interface, the later is unified with the industry leading IMC coverage environment from Incisive. Significant productivity is achieve by organizing the metrics against a verification plan( vPlan), effectively back annotating results to your goals. vManagerTM then supports tracking of progress over time and has built in chart creation utilities to visualize status of any metric contained in the SQL database. Charts, Regression and vPlan results can then produce clickable HTML reports which can also be displayed over the web as dashboards. Last, thru a powerful API, vManagerTM can also integrate with popular external enterprise tools, such as continuous integration tools like Jenkins, or bug tracking tools such as Bugzilla.

Roxan Saint-Hilaire is Applications Engineering Director at Cadence. He and his team of verification AEs focus on deployment and training of advanced software and hardware verification solutions in Silicon Valley. Roxan has over 15 years of verification experience using languages like Vera, Specman 'e', SystemVerilog and deploying methodologies like eRM, OVM and UVM. Roxan holds a BSEE from Ecole Polytechnique of Montreal and an MBA from the Haas School of Business at UC Berkeley.