Join us on Wednesday, December 7th for a festive holiday lunch, networking, presentations by Thinh Ngo, Broadcom, and Eldon Nelson, Intel.
Tutorials by OneSpin Solutions, ARM and Cadence.
We look forward to seeing you there!
|11:30am||Doors Open / Networking|
|12:00pm - 12:25pm||Thinh Ngo presents "Accelerate Your Testbench Development Time With a Hybrid Testbench"|
|12:25pm - 12:50pm||Eldon Nelson presents "Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"|
|12:50pm - 1:10pm||Networking|
|1:10pm - 1:40pm||
Tutorial 1: Making Formal Friendly for Simulation Savvy Engineers (OneSpin Solutions)
Presentation by Thinh Ngo, Broadcom:
Accelerate Your Testbench Development Time With a Hybrid Testbench
A hybrid testbench is a top-level testbench upon which a block-level testbench is piggy-backed. It can work in either a top-level testbench alone or a combined top-level and block-level testbench mode. In combined mode, block-level stimulus generators use force statements to override existing signal values with constrained-random stimuli to exercise buses, arbiters and memories which are mainly exercised via directed tests from attached processors in the top-level testbench. Hybrid testbench excludes the need to create a separate block-level testbench while efficiently makes use of existing infrastructure of top-level block testbench. Specifically, the integrated block-level testbench will reuse clocks, resets, assertions, checkers of the top-level testbench. Particularly, it does not need to create responder BFMs (e.g. for arbiters, buses) since they are already available as RTL. Additionally, hybrid-testbench can help speed up simulation as its forced interface can replace slow RTL logic. Finally, it can facilitate verification of incomplete design by replacing incomplete logic with its forced interface. The integrated block-level testbench typically comprises an interface, an agent, a sequence, and a driver.
Thinh Ngo is a principal design verification engineer of Broadcom Limited, and has more than 12 years of experience in design verification. Thinh has verified DSPs, caches, multi-core SoCs, ARM processor subsystems and firmware, and has published 8 papers in design verification. Thinh graduated with a BSEE from Oklahoma State University and a MSEE from Stanford University.
Presentation by Eldon Nelson, Intel:
"Design Patterns by Example for SystemVerilog Verification Environments Enabled by SystemVerilog 1800-2012"
“Design Patterns”, published in 1994, is widely seen as popularizing the idea of software design patterns. The book contained explanations and applications of software design patterns and gave them their definitive names. The missing component to actual implementation of many of the design patterns in SystemVerilog is language support, which has only recently become available with the release of the SystemVerilog 1800-2012 specification. This presentation will realize design pattern examples from the book “Head First Design Patterns”—originally written in Java—and port them to SystemVerilog while being as true to the original implementation as possible. The goal will be to expose that many design patterns are now possible to implement in SystemVerilog 1800-2012. Applications of those design patterns tailored to verification environments is demonstrated to show its usefulness.
Eldon Nelson is a Verification Engineer working at Intel. He received his B.S. and M.S. degree in Electrical Engineering from the University of Minnesota and is a licensed Professional Engineer (P.E.). Eldon's technical blog: tenthousandfailures.com features posts on verification and GNU Emacs - two of his favorite topics. He has had opportunities to serve as a volunteer within the Institute of Electrical and Electronic Engineers (IEEE) in a variety of positions and is presently serving as the elected IEEE Twin Cities Secretary. He has one US patent currently granted and has three published papers in verification. Before working at Intel, he has worked for: Micron Technology, IBM and the National Science Foundation.
"Making Formal Friendly for Simulation Savvy Engineers"
Are you a Simulation user who is interested in how Formal might be used to improve verification, but has not had the time to get involved with assertion authoring? If so, this tutorial is for you.
Operational Assertions (OA) makes use of standard SystemVerilog, but allow the writing and testing of assertions in an abstract, easy to understand, simulation-centric fashion. In this design example based, 1.5 hour tutorial we will show how to easily verify key blocks without the hassle of deep SVA by using OA, quickly create test scenarios that otherwise require hours of UVM stimulus coding, and track down tricky bugs, all by the simple application of Formal. We’ll also show you how to tie the formal results back into your UVM tests, simulation coverage data, and debug environment. Formal experts, if you want to pick up some novel assertion techniques, this is a great presentation for you as well.
Sven Beyer—Technical Manager, OneSpin
Sasa Stamenkovic—Application Engineer
Virtual Prototyping with ARM SoC Designer for IP Selection and Architectural Exploration
Are you one of the many verification engineers finding yourself working on more and more ARM-based SoC’s? If so, you’re definitely not alone. This tutorial, presented by ARM, will give an overview of the ARM Cycle Model analysis tool “SoC Designer”. While this tool is intended to be used more by system architects to perform IP selection and configuration, performance analysis and firmware development, getting a better feel for these high-level considerations and trade-offs can be extremely helpful to the verification engineer. Understanding at this level can certainly provide better understanding to how these systems work, or in some cases how they’re ‘supposed’ to work.
Rayfes Mondal, Cycle Models Core Comp FAE - ARM
High-Speed Software-Driven SoC Verification with Parallel Simulation
If there’s one aspect of verification that never changes, it’s the need for speed. The third-generation high-speed Rocketsim parallel simulator from Cadence is an industry breakthrough in terms of simulation performance. Maximum speed-up requires a test bench built for speed, and the tests generated automatically by the Cadence Perspec software-driven verification solution are ideal for the Rocketsim parallel simulator. Since the embedded processors within the system-on-chip (SoC) are leveraged as part of the Perspec SW-driven verification environment, many slow testbench components can be reduced or eliminated. Perspec-generated tests support UVM-compliant verification IP (VIP) and accelerated VIP (AVIP). The combination of Rocketsim technology and Perspec tests supports an important new SoC verification methodology that is fully aligned with the emerging Accellera Portable Stimulus Standard (PSS). This tutorial will show hands-on verification engineers how to take advantage of this powerful methodology today.
Venkataramana (Reddi) Reddipalli
Reddi is is an Applications Engineer with Cadence Design Systems in Austin TX. He has been with Cadence for more than 10 years working with customers to deploy advanced IP and SoC verification solutions on simulation and hardware emulation platforms. As part of this work, Reddi has developed a lot of expertise in Metric-Driven UVM based test benches and has started ramping up on SW-Driven verification environments. Before joining Cadence, Reddi worked as an Applications Engineer at Verisity, which he joined as part of the Axis Systems acquisition where he started his career.