Please join us for the next DVClub Silicon Valley event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.

For this event David Brownell from Analog Devices will be presenting "Portable Stimulus: The Next Step in Verification Productivity." We will also feature a tutorial after lunch by OneSpin Solutions, entitled “Making Formal Friendly for Simulation Savvy Engineers.”

We look forward to seeing you there!

Wednesday, October 12, 2016 from 11:30 AM to 1:50 PM

Dave and Buster's
940 Great Mall Drive
Milpitas, CA 95035
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Agenda

11:30am Doors Open / Networking
12:00pm Lunch and Presentation by David Brownell, Analog Devices
12:50pm

Networking

1:10pm Tutorial by OneSpin Solutions

Registration Now Open - Click to RSVP 

 Keynote Presentation: "Portable Stimulus: The Next Step in Verification Productivity"

During the product development lifecycle the verification of IP blocks, subsystems, SOCs and actual silicon is performed by different teams using a variety of programming languages and platforms. The same verification task is often duplicated multiple times by multiple teams, resulting in a massive duplication of effort, false bug reports, and delayed time to market.

The EDA industry has recognized this growing problem and several companies have developed tools allowing the development of tests that can be re-used both horizontally and vertically. In addition, the Accellera Systems Initiative is actively drafting a “Portable Stimulus” standard proposing semantics and syntax for specifying verification intent and behavior that will be reusable across multiple target platforms.

This talk will cover my view on exactly what “Portable Stimulus” means, how PS can solve some of your big DV challenges, why the upcoming standard is so important, and encourage attendees to get involved with the PSWG.

About the Speaker: Dave Brownell

David Brownell is the manager of the Design Verification Methodology Team at Analog Devices. This team is focused on improving the ADI’s Design Verification capabilities and infrastructure. DVMT team members support engineers across ADI with integrating new tools and techniques into their development flow, and work with teams to solve their unique verification

David studied Computer Engineering and Mathematics at Tufts University and began his career at ADI in 1997 as a Product Test Engineer working on the SHARC family of DSPs. In 2006, David moved into Design Verification, where he has since worked on the verification efforts for multiple DSP processor families and, more recently, on Mixed Signal SOCs targeted for industrial, automotive, and consumer markets.

 

Tutorial: "Making Formal Friendly for Simulation Savvy Engineers"

Sven Beyer—Technical Manager, OneSpin
Sasa Stamenkovic—Application Engineer

Are you a Simulation user who is interested in how Formal might be used to improve verification, but has not had the time to get involved with assertion authoring? If so, this tutorial is for you.

Operational Assertions (OA) makes use of standard SystemVerilog, but allow the writing and testing of assertions in an abstract, easy to understand, simulation-centric fashion. In this design example based, 1.5 hour tutorial we will show how to easily verify key blocks without the hassle of deep SVA by using OA, quickly create test scenarios that otherwise require hours of UVM stimulus coding, and track down tricky bugs, all by the simple application of Formal. We’ll also show you how to tie the formal results back into your UVM tests, simulation coverage data, and debug environment. Formal experts, if you want to pick up some novel assertion techniques, this is a great presentation for you as well.


At the end of the event we invite you to stay for free cocktails and drone raffle with our experts, including the OneSpin CEO Raik Brinkmann.