As summer winds down and football season starts up, it's time once again for another DVClub lunch. As always, this is a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Come catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible.

Of course you tell your boss that keeping you around will save him money in the long run because of all the bugs you find, right? Conventional wisdom is that bugs cost 10X more at each development stage. This is often cited to justify tool purchases and methodology changes. Where does that 10X come from? And if we have actual data about the cost of bugs, how can it help? Ken Albin from Oracle will be here to answer these questions and more with his presentation "The Cost of SoC Bugs." Perhaps you might even get the ammunition you need for that next big raise!

In addition to the lunchtime presentation from Ken, we have an optional tutorial immediately following for those who wish to stay and enhance their skillset. Avery Design Systems will be teaching how to improve “Gate Simulation signoff” throughput by handling the noise from False X’s.

This will be another awesome event, we look forward to seeing you there!

Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, Sep. 7, 2016 from 11:30 AM to 1:30 PM (CST)
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11:30am Doors Open / Networking

Lunch and Feature Presentation

  • Ken Albin - The Cost of SoC Bugs


1:10pm Tutorial by Avery Design Systems - Improving 'Gate Simulation Signoff' throughput by handling the noise from False X's

Registration Now Open - Click to RSVP

"The Cost of SoC Bugs"

About Ken Albin:

Ken Albin is a Senior Design Verification Engineer and Toolsmith at Oracle Labs in Austin, Texas.

After earning an MSEE degree at Kansas State University, Ken worked in the Processor Technology department at Rockwell-Collins in Cedar Rapids, Iowa; formal verification research firm Computational Logic Inc; on advanced verification tools and methodology at Motorola/Freescale Semiconductor; at AMD focusing on verification methodology; and at Intel in the Front End Design Automation group working with low-power CPU and SoC design teams.

Ken has been working in design verification since before they called it design verification.

"Improving 'Gate Simulation Signoff' throughput by handling the noise from False X's"

For companies that are using gate simulation to verify functionality, many already understand that despite efforts to clean up potential “X” issues in RTL, their post-synthesis and optimization results can produce additional sources of “X” in their gate netlist. Some of the effects of the “X”s in gate simulation are not real, but are mainly artifacts of Verilog simulation being overly pessimistic. As design and verification engineers race against the clock to analyze the results to find real problems, the noise created by the false X’s can cause too much time wasted. As such, some companies have more brute force methods, such as initializing all flops to some artbitrary value and run multiple simulations to hope they have not masked a real issue.

About Avery Design Systems:

Avery Design Systems has had a product on the market for many years, SimXACT, to help the companies take a more conservative approach to removing the noise from false X’s, by applying the tool dynamically during simulation to remove those false X’s and using formal analysis to prove the correctness of the fixes.