Before you pack up the station wagon, load up the kids, and head to Wally World for that upcoming summer vacation, it's time once again for another DVClub lunch. As always, this is a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Come catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible..

Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, March 9, 2016 from 11:30 AM to 1:30 PM (CST)
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For this event we are pleased to present two different speakers. First up we have Stan Sokorac from ARM who will be presenting "Systemverilog Interface Classes: More Useful Than You Thought." Interface classes are a relatively new addition to SystemVerilog, and are not the same thing as virtual interfaces, which just about everybody already uses. Although not that many people know how to use SystemVerilog interface classes, don't worry! Stan is here to help keep us on the cutting edge (and perhaps help you impress your boss and co-workers).

Our second speaker will be Zhipeng Ye who will be driving down from TI in Dallas to present "Functional Coverage Collection for Analog Circuits." 'What!' you say? 'You can do functional coverage with analog?'. Indeed you can, and Zhipeng will be here to explain how it's done.

Two very different presentations, both fantastic, and there's sure to be something for everybody. We look forward to seeing you there!

Agenda

11:30am Doors Open / Networking
12:00pm

Lunch and Presentations

  • Stan Sokorac - Systemverilog Interface Classes: More Useful Than You Thought
  • Zhipeng Ye - Functional Coverage Collection for Analog Circuits
1:00pm-1:30pm Networking

Registration Now Open - Click to RSVP

"Systemverilog Interface Classes: More Useful Than You Thought"

Stan Sokorac - About the Presenter:

Stan Sokorac is a Computer Engineering graduate from University of Toronto, and has worked at IBM, ATI, AMD, and ARM, in various roles including software development, ASIC design, verification, and management. He is currently a Sr. Principal Design Engineer at ARM, driving verification of the cache coherent memory subsystem on the next-generation ARM® Cortex-A® CPU core. He is passionate about introducing new methodologies and developing new flows that improve verification efficiency and effectiveness.

About the Presentation:

Interface classes were introduced in SystemVerilog 2012, but have seen little adoption in the verification community. While this construct is well established in the software development world, most verification engineers either don’t know about it or don’t see any benefit in using it. The goal of this presentation is to demonstrate the value of interface classes by sharing some of the most important uses which were employed during the verification of the next-generation ARM® Cortex-A® CPU core.

 

"Functional Coverage Collection for Analog Circuits"

Zhipeng Ye - About the Presenter:

Zhipeng Ye is a verification lead in Texas Instruments in Dallas TX. Before joining TI, he worked for Maxim Integrated in Chandler Arizona and Australia Semiconductor Technology Company in Adelaide Australia. He holds a Ph.D. degree from University College Cork, Ireland.

About the Presentation:

Abstract-In this presentation, Analog Coverage Collector (ACC) is proposed to serve as a tool that analog designers can utilize to pass the analog design information, even when this information is deep inside the schematic hierarchy, to verification engineers who would handle chip level AMS/functional testbench for mixed signal designs. Based on that information, verification engineers are able to construct meaningful covergroups at the top level testbench in order to measure the chip-level functional coverage as accurately as possible. We show that analog designers can easily use ACC, and an example is presented to demonstrate the flow to collect analog coverage.