Please join us in Toronto for this exciting DVClub event! You will be treated to a complimentary catered lunch while you network with industry collegues, and enjoy an enlightening presentation.
For this event Bruno Bratti from Wave Semiconductor will be presenting "AXI HW/SW Verification for FPGA." Immediately following the main event we are also pleased to sponsor a free optional tutorial by well-known industry guru Stuart Sutherland. Stuart's presentation is entitled "Adopting SystemVerilog UVM – A Technical Examination of the SystemVerilog Universal Verification Methodology (UVM), When it is the Right Choice to Use, and What is Needed to Successfully Adopt UVM", you'll definitely want to stick around for it.
We look forward to seeing you there!
Wednesday, January 27 2016 from 11:30 AM to 1:30 PM
Portland Community College (PCC) Willow Creek Center
241 SW Edgeway Drive
Beaverton, OR 97006
|11:30am||Doors Open / Networking|
|12:00pm||Lunch and Presentation|
|1:15pm-2:00pm||Tutorial: Adopting SystemVerilog UVM – A Technical Examination of the SystemVerilog Universal Verification Methodology (UVM), When it is the Right Choice to Use, and What is Needed to Successfully Adopt UVM|
Keynote Presentation: "AXI HW/SW Verification for FPGA"
With FPGA designs approaching SOC levels of complexity, AXI has become the leading interconnect for IP in large FPGA projects. A significant portion of any AXI design involves software driving the interconnect. This presentation covers the basics of AXI and shows how to leverage DPI to verify the same software code in an FPGA as well as in simulation.
About the Speaker:
Bruno Bratti is a Principal Engineer at Wave Semiconductor. After graduating with an honors degree in Computer Engineering from the University of Waterloo he began his career at Avici Systems, as an ASIC Engineer. For the last 15 years Bruno has held various roles in both the EDA and ASIC industries, with a focus on Emulation and SOC Verification.
Tutorial: Adopting SystemVerilog UVM – A Technical Examination of the SystemVerilog Universal Verification Methodology (UVM), When it is the Right Choice to Use, and What is Needed to Successfully Adopt UVM
Is UVM right for my projects? This one-hour technical seminar is for lead ASIC/FPGA and custom IC design and verification engineers and engineering managers, and will help answer that question. The seminar will be presented by Stuart Sutherland, an independent industry expert in SystemVerilog. The seminar is not a simple marketing overview! The seminar will provide an in-depth examination of the nuts and bolts of a UVM testbench, including writing stimulus generators, drivers, monitors, and scoreboards. The overarching goal of the seminar is to provide decision makers an accurate understanding of the capabilities of the UVM verification methodology, and what is required to implement this methodology in current or future engineering projects. Both the strengths and weaknesses of UVM will be presented, as well as a candid look of what factors need to be considered for determining when UVM is a good solution and when it might be the wrong choice for a verification project.
About the Speaker:
Stuart Sutherland is an independent SystemVerilog consultant who specializes in providing training in SystemVerilog and UVM. Stu’s career with Verilog began in the 1980’s, when he worked for the company that created the Verilog HDL and the first Verilog simulator. He is actively involved in the IEEE SystemVerilog and UVM standards process, and has been a technical editor for every version of the IEEE Verilog and SystemVerilog standard.