We are pleased to once again join forces with MTV 2015 for our December event. This time around we'll hear from two of our local Austin colleges, Ram Narayan and Tom Symons from Oracle Labs. Their presentation is titled "I created the Verification Gap."

In addition to our usual lunch, networking, and presentation, we will also feature optional tutorial sessions following the main presentation. Feel free to stay for just the lunch presentation, or stick around and enjoy the free tutorials put on by industry leaders. We look forward to seeing you there!

Agenda

11:30am Doors Open / Networking
12:00pm Lunch and Presentation
1:00pm Networking
1:15-2:15pm Tutorial 1: Virtual Platform technology for ESL Design and Verification
  Tutorial 2: How A Generic Hardware Debug IP Can Help with Silicon Debug

 

Registration Now Open - Click to RSVP

12:00pm: Lunch and Presentation: I created the Verification Gap

Speakers:

Ram Narayan and Tom Symons are both senior verification engineers working for Oracle Labs' Hardware Advanced Development group in Austin, Texas.

Abstract:

It is widely accepted that the productivity gap between design and verification exists and is widening. This presentation explores the various factors that contribute to this Verification Gap. While touching on factors like growing design complexity that inherently cause the gap, the focus of the presentation will be on those factors that are self-induced and hence within our control. Experiences of individuals in the industry have been sought, digested and will be shared as part of the presentation. The objective here will be to evoke a sense of individual responsibility in the attendees through self inquiry.

1:15-2:15pm: Tutorial Session 1: Virtual Platform technology for ESL Design and Verification

Speakers:

Magdy El-Moursy, Ashraf Salem, Mentor Graphics. Egypt

Abstract:

Virtual Platforms are emerging as the key technology to build virtual prototyping for real products. Virtual Platforms (VP) reduce Time to Market for SoC, Embedded Systems, and Automotive Applications. VPs enable fast architecture exploration, early Software (SW) development, and efficient performance analysis. Software engineers have little experience dealing with real Hardware. On the other hand, Hardware engineers know little about SW stacks. Virtual Platform technology aim to relief the pain in the interaction between those two worlds. Having a model for the real HW allows SW engineers to start their development early enough to meet the tight schedule of a product.

Virtual Platforms have incomparable debug and analysis capabilities which do not exist in real HW or in HW prototypes. Non-Intrusive tracing is one of the unique attributes of VPs. With VPs, SW and HW can be traced and debugged simultaneously and within the same setup environment. SW stacks can now be debugged while interacting with functionaly accurate HW models. Transaction Level Modeling and SystemC, as now being more matured methodologies, are the primary enable knobs for VPs. The number of commercial tools to build VPs is increasing everyday. The technology is being adopted in many industries. Operating Systems (OS) can now be loaded to virtual targets enabling a very close to real framework for SW development.

Automotive applications are among the most complex applications which require high abstraction model for the underneath HW. AutoSar is now the standard for building SW for many Automotive industry. VPs would enable reducing the development cycle of AutoSar/Automotive applications.

In this tutorial, the Virtual Platform technology for Electronic System Level Design and Verification is presented. The key languages and tools to build VPs are summarized. The flow to develop VPs is also provided. The analysis capabilities with different case studies are presented. How VPs can enable early SW development and architecture exploration for Automotive/AutoSar applications is also demonstrated.

About the Speakers:

Magdy El-Moursy

He received the B.S. degree in electronics and communications engineering (with honors) and the Master's degree in computer networks from Cairo University, Cairo,Egypt, in 1996 and 2000, respectively, and the Master's and the Ph.D. degrees in electrical engineering in the area of high-performance VLSI/IC design from University of Rochester, Rochester, NY, USA, in 2002 and 2004, respectively.

In summer of 2003, he was with STMicroelectronics, Advanced System Technology, San Diego, CA, USA. Between September 2004 and September 2006 he was a Senior Design Engineer at Portland Technology Development, Intel Corporation, Hillsboro, OR, USA.
During September 2006 and February 2008 he was assistant professor in the Information Engineering and Technology Department of the German University in Cairo (GUC), Cairo, Egypt.
Between February 2008 and October 2010 he was Technical Lead in the Mentor Hardware Emulation Division, Mentor Graphics Corporation, Cairo, Egypt.

Dr. El-Moursy is currently Staff Engineer in Design Creation and Synthesis Division, Mentor Graphics Corporation, and Associate Professor in the Microelectronics Department, Electronics Research Institute, Cairo, Egypt. He is Associate Editor in the Editorial Board of Elsevier Microelectronics Journal, Journal of Circuits, Systems, and Computers, and International Journal of Circuits and Architecture Design and Technical Program Committee of many IEEE Conferences such as ISCAS, ICAINA, PacRim CCCSP, ISESD, SIECPC, and IDT.

His research interest is in Networks-on-Chip/System-on-Chip, interconnect design and related circuit level issues in high performance VLSI circuits, clock distribution network design, digital ASIC circuit design, VLSI/SoC/NoC design and validation/verification, circuit verification and testing and low power design. He is the author of more than 60 papers, five book chapters, and two books in the fields of high speed and low power CMOS design techniques and NoC/SoC.”

Ashraf Salem

Ashraf Salem is Engineering Director in Mentor Graphics Egypt. He manages a group of 140 engineers working in the development of Emulation, Simulation and Embedded Systems products. Dr. Salem obtained his Ph.D. from Grenoble University, France in 1992. He got his B.Sc. and M.Sc. in Computer Engineering from Ain Shams University in 1983, 1987 respectively.

He was the CEO of the Technology Innovation and Entrepreneurship Center (TIEC) and professor of Computer Engineering, Faculty of Engineering, Ain Shams University. Dr. Salem participated in the establishment of ANACAD branch in Egypt in 1995 that then has been acquired by Mentor Graphics and became one of the largest multinational development centers. Dr. Salem is on the Board of the trustees of Information Technology Institute and he participated in the establishment of Software Engineering Competence Center in Egypt

He published more than 100 scientific articles in the fields of Computer Aided design of Digital circuits. He chaired the technical committees in a number of international conference, and he supervised more than 20 PhD and M. Sc. thesis in digital design and Embedded systems. Also, he participated in a number of international research projects and developed one of the pioneer research product for circuit verification in the eighties.

 

1:15-2:15pm: Tutorial Session 2: How A Generic Hardware Debug IP Can Help with Silicon Debug

Speakers:

Mark LaVine, ARM Inc

Abstract:

 Debugging SoC simulation test failures can be challenging, but internal design visibility greatly decreases from simulation which has full visibility to silicon which has almost no visibility. Also design and verification teams are challenged with aggressive goals/schedules and typically do not have the time or resources to develop DFD (design for debug) capabilities that would improve visibility for silicon debug. This tutorial describes the challenges that can occur when debugging silicon and proposes a generic DFD solution that could be attached to any IP to improve visibility with low design/verification overhead, isolate the area of failure, and thus reduce the overall average time for debugging silicon issues.

About the Speaker:
Mark LaVine is a technical lead at ARM for silicon validation of test chips and the development of hardware debug solutions. Mark has past experience at other companies in a range of other areas which includes design, processor and SoC verification, silicon validation, test and process.