DVClub Silicon Valley – October 10, 2018 – Presenter: Mark Glasser (NVIDIA)
Please join us on October 10, 2018 at Dave and Buster’s for a catered lunch and networking. Mark Glasser, a Principal Verification Architect at NVIDIA, will be presenting.
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch / Presentations by Mark Glasser (NVIDIA)
- 1:00pm — Networking
“Generic Programming in SystemVerilog” by Mark Glasser, NVIDIA
Making programs generic, or generic programming, means making programs independent of information about types, sizes, locations, and similar specific information. This requires certain programming styles and language features which avoids coding low-level details. SystemVerilog, with its heritage as a hardware modeling language, has some features for generic programming but is not considered a generic programming language.
We have developed the SystemVerilog Extension (SVX) library which provides facilities that improve the capability of SystemVerilog to render generic programs. SVX is written entirely in standard SystemVerilog with no reliance on DPI or any other external interface.
Aspects of generic programming are discussed, including removal of assumptions and abstraction.
We give a tour of the library and its facilities and features. Then we discuss concepts of generic programming in terms of SVX. Finally, we compare our work with others who have approached the same topic and describe some future directions for generic programming in SystemVerilog.
How are we to directly verify the source HLS model? Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog. This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.
- Mark Glasser has is currently a Principal Verification Architect at NVIDIA Corporation. His verification work includes such things as architecture of UVM-based testbenches, including multi-lingual, multi-abstraction testbenches, and verification of safety critical systems. His technical interests include tools and methodologies for verifying electronic systems. Mark holds a Bachelor of Science in Computer Science from California State University, Northridge.
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