DVClub Silicon Valley – November 8, 2019 – Guest Speakers: James Gorman (Ericsson), Glenn Canto (Ericsson), & Rich Edelman (Mentor)
Please join us on November 8, 2019 at Dave and Buster’s for a catered lunch and networking.
We are very fortunate to have THREE presentations at this event! James Gorman, a System Lead and Architect for CPU Subsystems at Ericsson, Glenn Canto, a builder of virtual platforms at Ericsson, and Rich Edelman, a Verification Technologist at Mentor, a Siemens Business, will be presenting.
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch / Presentations by James Gorman, Glenn Canto, and Rich Edelman
- 1:30pm — Networking
“What is 5G?” by James Gorman (Ericsson)
Everybody is talking about 5G, but not everyone knows what it really means. Come learn about some key technical features and what it means for users. Built on latest technologies, hear how Ericsson’s architecture brings new semiconductor design and verification challenges and about how we’ve addressed them.
- James Gorman is a System Lead and architect on the CPU Subsystem team at Ericsson ASIC Design Center in Austin, Texas. In his role, he architects on-chip multi-core CPU subsystems for 5G baseband and radio ASICs. Previously, he worked as a Senior hardware engineer at National Instruments for several years, after graduating with a Masters in Electrical Engineering from University of Colorado, Boulder. Outside of work, you can find him hitting the trails around Austin, rock climbing and volunteering at Habitat for Humanity.
“Effective Reuse Through Virtual Platforms at Ericsson” by Glenn Canto (Ericsson)
Virtual platforms are frequently used only as a stopgap solution for facilitating pre-silicon software development, but there is often overlooked potential for reuse in verification environments. Similarly, by providing quality tools to our software developers, the virtual platform becomes reusable post-silicon. We will describe our virtual platform, it’s integration with our hardware verification environment and dynamic analysis tools supporting software development.
- Glenn Canto builds virtual platforms for Ericsson’s many core baseband ASICs. There he is responsible for accelerator IP modeling and system integration. Glenn enjoys creating tools to enable productive software developers. Previously, he has experience with performance modeling and analysis of on chip interconnects and ethernet networking.
“UVM – Where Are We? Is it Safe?” by Rich Edelman (Mentor, a Siemens Business)
The UVM has been around for years, and gone through many versions, and is now an IEEE standard. But the question remains – Where Are We? Join us for a quick flash through verification techniques over the years from Verilog “input/expected output” to PLI to vera and e to SV and DPI to UVM. We’ll spend time on a variety of UVM functionalities, including UVM Config, UVM Transaction Recording, UVM Registers and the Out-of-Order transaction issue. At each point we’ll ask “Where are we”? Do we need changes? Do we just need to make the code “Safe”? We’ll talk about the past, the present and the future of the UVM.
- Rich Edelman is a Verification Technologist specializing in helping customers adopt and deploy the UVM. Rich has worked in ASIC companies, EDA consulting, EDA start-ups, and 2 of the big three. Rich first got involved with the UVM while developing his “RPS training class”, which was an easy way for people to learn about the methodologies. Rich’s verification interests range from DPI and transaction recording to register modeling, sequences and class-based debug. Rich has published many related conference papers, including a Best Paper on SystemVerilog DPI at DVCON, and various transaction recording papers with IPSOC. Rich received a BSEE, a BSCS and an MSCS from Washington University in St. Louis.
RSVP and invite some of your colleagues!