DVClub Fort Collins – June 27, 2019 – Presenters: Harry Foster (Mentor), Cliff Cummings (Sunburst Design), & Dave Burgoon / Mike Erickson (Microsoft)II
Please join us on June 27, 2019 at the Fort Collins Marriott for a catered lunch and networking. We are excited to announce that we will have three presentations for this event: Harry Foster, Chief Scientist Verification at Mentor / Siemens, Cliff Cummings, President of Sunburst Design, Inc., and Microsoft’s Dave Burgoon (Senior Design Verification Engineer) & Mike Erickson (Principal Engineer) will all be guest speakers!
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch & Presentations by Harry Foster, Cliff Cummings, Dave Burgoon / Mike Erickson
- 1:30pm — Networking
“UVM for IP Designers: Moving Toward “Killing two birds with one stone” by Dave Burgoon & Mike Erickson, Microsoft
In our hardware IP development methodology, designers typically put together a simple module-based directed-stimulus testbench to do the initial “bring up” of their RTL model, in an effort to verify basic functionality before handing off the design to a verification engineer for official sign-off verification. The verification engineer typically starts over and develops a constrained-random testbench using UVM. Often, due to the limited coverage of the bring-up testbench, we find ourselves in the unhappy situation of attempting to simultaneously turn on, by way of the UVM testbench, three pieces of non-trivial code: the Verilog RTL model, the UVM testbench, and the C++ golden reference model consulted by the UVM scoreboard. We began to wonder if there was a smarter way of working. Could we achieve more coverage at the bring-up stage by making UVM accessible and palatable to RTL designers, and then leverage the bring-up testbench as the starting point for the sign-off testbench? Would a testbench code generator tool help make UVM more accessible to designers? Our presentation summarizes our experience to date in pursuing these questions.
- Dave Burgoon has a B.S. in Electrical Engineering, summa cum laude, from the University of Toledo, and an M.S. in Computer Science from Colorado State University. He has two U.S. patents, and has made various contributions over the years to industry conferences and publications, including DVCon, its predecessors (IVC/VIUF and HDLCon), DesignCon, and the Design Automation Conference. Dave is a Senior Member of the IEEE, and has over 37 years of experience in hardware design, verification, and functional modeling. He is presently a Senior Design Verification Engineer on Microsoft’s Custom Silicon Development team, which develops SoCs, chipsets, and sensors for Xbox, HoloLens, Azure cloud accelerators, and other devices.
- Mike Erickson has 22 years of experience leading hardware development efforts in servers, storage, image processing, display pipelines, and neural networks. He holds 20 U.S. patents, with 4 patents pending. Mike is currently a Principal Engineer in Microsoft’s Silicon Development team, working on HoloLens and Azure cloud hardware acceleration.
“UVM Analysis Port Functionality and Using Transaction Copy Commands” by Cliff Cummings (Sunburst Design, Inc.)
There is significant confusion surrounding UVM analysis ports and similar confusion about the UVM transaction copy command. Many verification engineers who consider themselves to be UVM experts can easily spend hours debugging analysis port issues if they are unaware of important considerations related to analysis port paths.
This presentation explains UVM analysis port usage and compares the functionality to subscriber satellite TV. The presentation shows simplified, non-UVM, analysis port implementations to clarify how the corresponding UVM port connections work. The presentation describes how the analysis port write() method efficiently calls each subscriber’s write() method. Part of the explanation describes when an analysis implementation port requires the use of a transaction copy() command.
- Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training. Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted “Best Paper.” Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.
“Industry Trends in Functional Verification” by Harry Foster of Mentor, A Siemens Business
In this talk, Harry Foster presents the findings from the 2018 Wilson Research Group Functional Verification Study. The findings from this large double-blind industry study provides invaluable insight into the state of today’s IC/ASIC and FPGA markets in terms of both design and verification trends, and should help design projects benchmark their on process maturity with the overall industry.
- Harry Foster is Chief Scientist Verification for the IC Verification Solutions division of Mentor, A Siemens Business; and is the Co-Founder and Executive Editor for the Verification Academy. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.
RSVP NOW and invite some of your colleagues as well!