DVClub Boston – May 29, 2019 – Presenter: Jeremy Ridgeway
Please join us on May 29, 2019 at the Westford Regency for a catered lunch and networking. Jeremy Ridgeway of Broadcom will be our guess speaker.
- 11:30am—Door Open / Networking
- 12:00pm—Lunch / Presentation by Jeremy Ridgeway of Broadcom
“Want Functional Coverage Closure? Don’t Kneel Before the Almighty Random Constraint Solver”
Previously, a testplan matched one-for-one to tests implemented in the testbench. A passing test meant the testing scenario was verified. With the onset of constrained random verification and its limited test suite, we have achieved a reversal of correlation: one test run equals many testing scenarios. Function coverage, reported from within the testbench, monitors our verification progress. We have also achieved a gap: testing scenarios we want to cover versus testing scenarios actually covered (reality). Instead of simply running more tests, why not nudge randomization towards our goals first? Cover our testplan and then let the constraint solver do its magic. We present our SystemVerilog random variable container class library that enables exactly that: random variables with the flexibility to manipulate the constraint, or even to instantiate a totally new constraint, during simulation and without recompilation. Coupled with a string parser with access to the UVM configuration database and command-line plusargs, constraints may be provided from anywhere in the testbench or on the simulation command-line. However, the external test or sequence need not intervene as the random variable can autonomously manipulate its constraint to disallow random streaking. Already hit that coverbin value? Great! The variable can make sure that value (or predicate) won’t happen again until all desired bins are hit. Challenges still remain but leaving our program’s fate to the constraint solver doesn’t need to be one of them.
- Jeremy Ridgeway has nearly twenty years of computer hardware verification experience at all levels of abstraction and is currently focused on PCI-Express subsystem level verification. His interests are in verification cycle management, test bench random variables, and functional coverage. Jeremy holds a BS in Computer Engineering from the University of Arizona, an MS in Electrical Engineering from the University of Alabama, and was, for a time, a PhD candidate in formal verification constraint solving at the University of Trento, Trento, Italy.
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