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DVClub Boston – August 1, 2018 – Dave Burgoon from Microsoft Presenting & Tutorial by Narayana Reddy from Cadence


August 1, 2018


11:30 am - 01:30 pm

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Westford Regency

219 Littleton Rd , Westford, MA 01886

Westford, MA, US, 01886

Please join us on August 1, 2018 at the Westford Regency for a catered lunch and networking. Dave Burgoon of Microsoft will be our guest speaker, and Narayana Reddy of Cadence will lead a tutorial on merging and analyzing simulation/emulation coverage databases.

  • 11:30am — Doors Open / Networking

  • 12:00pm — Lunch / Presentation by Dave Burgoon of Microsoft & Tuturial by Narayana Reddy of Cadence.

  • 1:00pm   — 1:30pm / Networking 


“UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs” by Dave Burgoon, Microsoft

HLS (High-Level Synthesis) tools allow us to raise the level of abstraction of our hardware design models from RTL (Register Transfer Level) written in Verilog to a much higher, untimed level written in C++.  These tools produce Verilog RTL models that are fed to conventional RTL-to-gates synthesis tools, the output of which flow into the physical design process.  The advantages of working at this higher level of abstraction are well-documented.  These include engineering productivity (e.g. fewer design coding errors), faster time to market, and the ability to quickly modify or leverage a design.

How are we to directly verify the source HLS model?  Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog.  This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.

  • Dave Burgoon has B.S. in Electrical Engineering, summa cum laude, from the University of Toledo, and an M.S. in Computer Science from Colorado State University.  He has two U.S. patents, and has made various contributions over the years to industry conferences and publications, including DVCon, its predecessors (IVC/VIUF and HDLCon), DesignCon, and the Design Automation Conference. Dave is a Senior Member of the IEEE, and has over 36 years of experience in hardware design, verification, and functional modeling.  He is presently a Senior Design Verification Engineer on Microsoft’s Custom Silicon Development team, which develops SoCs, chipsets, and sensors for Xbox, HoloLens, and other devices.



Cross-Domain Merging of Simulation and Emulation Coverage Databases by Narayana Reddy Lekkala of Cadence.

This is a short demo which explores merging multiple coverage databases from Incisive/Xcelium tests and Palladium tests.  In this demo, vManager is used to launch simulation and emulation jobs and to analyze metrics of merged coverage database.

  • Narayana Reddy Lekkala is a Senior Application Engineer at Cadence Design Systems where he works in the emulation team in a technical support role to help develop customer specific verification requirements.  He started working at Cadence after graduating from the University of Southern California in 2016.  In his spare time he enjoys playing soccer, reading, and traveling.


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