DVClub Austin – March 21 – Presenters David Borland (Amazon) & Kaushik Gopalakrishnan (ARM)
Please join us on March 21st at the Norris Conference Center for a catered lunch and networking. David Borland from Amazon will present, “EDA in the Cloud”, and Kaushik Gopalakrishnan will present, “Anvil – Multicore Memory Subsystem Verification Tool for Top-Level DV”.
- 11:30am — Doors Open / Networking
- 12:00pm — Lunch / Presentation #1 by David Borland from Amazon
- 12:30pm — Lunch / Presentation #2 by Kaushik Gopalakrishnan from ARM
- 1:00pm — Networking
“EDA in the Cloud“ by David Borland, Amazon
Breakthrough productivity: The cloud enables breakthrough productivity of design environments through the use of parallel elastic capacity and using the right machines for the right job. IP and SoC regression times have been reduced by 20X using environments that are seamless to the user through the use of on premise and cloud computing resources. Thinking big and thinking differently using the revolution of the cloud can dramatically change semiconductor development productivity.
- David Borland is Director of the Silicon Optimizations team at Amazon Web Services. Prior to joining AWS, he was a co-founder and the VP of Hardware Engineering of Calxeda which developed low-power ARM-based servers. David has also worked at Intel leading the Cellular and Application Processor engineering teams, was co-leader the Intel/ADI DSP joint development, and was product line manager at AMD working on cordless telephone and modem products. David is also a member of a number of Austin musical organizations (AustinJazzzBand.org…etc.), works with local high school bands, and is married with a son at Purdue.
“Anvil – Multicore Memory Subsystem Verification Tool for Top-Level DV“ by Kaushik Gopalakrishnan, ARM
ARM is the Architecture for a Smarter World, and today we find ARM cores ubiquitously in mobile phones. Soon we will find them in data centers and server farms. At the heart of these is an SoC that contains multiple clusters of ARM Cortex A-class application processors. Verification and coverage closure of a multi-core system is a big challenge, as the bugs are difficult to find and often found late in the design cycle. There are different approaches to multicore verification, but top-level RTL simulation is where coherency issues are more pertinent and easier to debug. We introduce Anvil, a Random Instruction Stream (RIS) generator for next-generation mobile and server-class processors, developed by ARM’s own Architecture & Technology Group. Anvil uses a constrained-random top-level approach to target memory subsystem components critical to multicore functionality, such as cache and memory hierarchy, cross-core coherency transactions, and the load store pipeline.
- Kaushik Gopalakrishnan is a Senior Design Engineer at ARM in Austin, TX. He is a developer on Anvil, a multi-core Random Instruction Stream (RIS) generator tool that is a product of ARM’s Architecture & Technology Group. Kaushik holds a Master’s degree in Computer Engineering from North Carolina State University and has been with ARM for 2-1/2 years. Prior to that, Kaushik worked for a short duration at Qualcomm and for two years at Cortina Systems in North Carolina.
Register now and bring your colleagues!