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DVClub Austin – June 19, 2018 – Presenters: Swami Venkatesan (Cadence), Dave Burgoon (Microsoft)

Details
Date:

June 19, 2018

Time:

11:30 am - 01:30 pm

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Organizer

DVClub

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Venue

Norris Conference Center

2525 W Anderson Ln #365, Austin, TX 78757

Austin, TX, US, 78757

Please join us on June 19, 2018 at the Norris Conference Center for a catered lunch and networking.  We are happy to announce that we have two presentations and a tutorial for this event:  Swami Venkatesan,  a Senior Architect at Cadence Design Systems, will give a presentation & tutorial on Portable Stimulus, and Dave Burgoon, a Senior Design Verification Engineer at Microsoft will give a presentation on functional verification of High-Level-Synthesis models.



  • 11:30am — Doors Open / Networking

  • 12:00pm — Lunch / Presentations & Tutorial by Swami Venkatesan (Cadence) & Dave Burgoon (Microsoft)

  • 1:30pm   — Networking


 


Presentation #1


“UVM for HLS: An Expedient Approach to the Functional Verification of HLS Designs” by Dave Burgoon, Microsoft


HLS (High-Level Synthesis) tools allow us to raise the level of abstraction of our hardware design models from RTL (Register Transfer Level) written in Verilog to a much higher, untimed level written in C++.  These tools produce Verilog RTL models that are fed to conventional RTL-to-gates synthesis tools, the output of which flow into the physical design process.  The advantages of working at this higher level of abstraction are well-documented.  These include engineering productivity (e.g. fewer design coding errors), faster time to market, and the ability to quickly modify or leverage a design.


How are we to directly verify the source HLS model?  Unfortunately, our present, unit-level simulation-based functional verification methodology library of choice, the Universal Verification Methodology (UVM), assumes that the model of the DUT (Design Under Test) is written in the same language as the library, namely SystemVerilog/Verilog.  This paper summarizes the scenarios we considered for dealing with this situation, and presents an expedient solution based on the UVM Connect open-source library.



  • Dave Burgoon has B.S. in Electrical Engineering, summa cum laude, from the University of Toledo, and an M.S. in Computer Science from Colorado State University.  He has two U.S. patents, and has made various contributions over the years to industry conferences and publications, including DVCon, its predecessors (IVC/VIUF and HDLCon), DesignCon, and the Design Automation Conference. Supercomputers.  Dave has over 36 years of experience in hardware design, verification, and functional modeling.  He is presently a Senior Design Verification Engineer on Microsoft’s Custom Silicon Development team, which develops SoCs, chipsets, and sensors for Xbox, HoloLens, and other devices.


 


Presentation #2


“Accellera Portable Stimulus Specification Explained” by Swami Venkatesan, Cadence Design Systems


Discover how the long-anticipated Accellera Portable test and Stimulus Specification (PSS) will impact your current working flow at the organization, automation, and individual levels. This presentation will walk you through the latest specification and give you a deeper understanding of its core concepts, focusing on teaching PSS and building a strong intuition for the standard value and its applications. We will review a spectrum of important SoC verification challenges and the PSS solution for each.



  • Swami Venkatesan is a Senior architect at Cadence with over 18 years for experience in SoC design and verification. He currently drives the SoC Verification methodologies across Simulation, Emulation, FPGAs and Post-silicon platforms and is in charge of worldwide deployment of Perspec Portable Stimulus solution. Prior to Cadence, Swami has worked with Intel and Wipro Technologies designing and verifying Processor and Network ASICs. Swami holds a Master degree in Technology from Indian Institute of Science, Bangalore.


 


Tutorial


“Perspec System Verifier and Portable Stimulus Standard in Action” by Swami Venkatesan, Cadence Design Systems


In this tutorial you will see PSS examples in action in Perspec System Verifier from Cadence. 



  • Swami Venkatesan is a Senior architect at Cadence with over 18 years for experience in SoC design and verification. He currently drives the SoC Verification methodologies across Simulation, Emulation, FPGAs and Post-silicon platforms and is in charge of worldwide deployment of Perspec Portable Stimulus solution. Prior to Cadence, Swami has worked with Intel and Wipro Technologies designing and verifying Processor and Network ASICs. Swami holds a Master degree in Technology from Indian Institute of Science, Bangalore.


 


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