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DVClub Austin – December 6 – Presenter: John Dickol (Samsung); Tutorial : Heath Chambers (HMC Design Verification/Sunburst Design)

Details
Date:

December 6, 2017

Time:

11:30 am - 02:00 pm

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Organizer

DVClub Austin

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Venue

Norris Conference Center

2525 W Anderson Ln #365, Austin, TX 78757

Austin, TX, US, 78757

Please join us on December 6th at the Norris Conference Center for a catered lunch and networking. John Dickol from Samsung Austin Research & Design Center (SARC) will present, “I Didn’t Know Constraints Could Do That!”, and Heath Chambers from HMC Design Verification, Inc. & Sunburst Design will give a tutorial entitled, “SystemVerilog & UVM Virtual Interfaces for Class-Based Training”.



  • 11:30am — Doors Open / Networking

  • 12:00pm — Lunch / Presentation by John Dickol of Samsung

  • 12:45pm — Networking

  • 1:00pm   — Tutorial by Heath Chambers of HMC Design Verification, Inc. & Sunburst Design


Presentation


I Didn’t Know Constraints Could Do That!” by John Dickol, Samsung Austin Research & Design Center


Abstract


Recent advances in SystemVerilog constraint solver performance make it practical to use more complex constraints in verification environments.  This presentation will review some lesser-known SystemVerilog constraint features (soft constraints, hierarchical constraints, array reduction constraints) and provide working examples of using these and other features to create constrained stimulus for complex real-world CPU/SOC verification problems such as testbench configuration, memory map allocation, etc.



  • John Dickol is a Principal Engineer at the Samsung Austin Research and Design Center (SARC) where he is currently developing verification tools and methodologies and looking for new ways to apply SystemVerilog constraints.  Before joining SARC, he led verification teams for SOC and DSP projects at MediaTek, Analog Devices, Intel, and IBM.  John has a BSEE from Lehigh University and a MSEE from Syracuse University.  He has 5 U.S. patents.


 


Tutorial


SystemVerilog and UVM Virtual Interfaces for Class-Based Testing by Heath Chambers, HMC Design Verification, Inc. & Sunburst Design


Abstract


Virtual interfaces are a common structure to tie a class-based testbench to a Design Under Test (DUT). This tutorial will describe the progression of virtual interface usage from simple virtual interface handle passing, to an OVM-like common storage object database to a UVM configuration database, how each works, and their advantages and disadvantages.



  • Heath Chambers is President of HMC Design Verification, Inc., a company that specializes in design and verification consulting and high tech training.  Heath has 20 years of ASIC and system verification experience, including 17 years teaching Verilog, SystemVerilog, UVM and synthesis with Cliff Cummings of Sunburst Design, and three years Specman Basic Training for Verisity.  Heath presented “How to Verify a Switch” at the first annual Verisity User’s Group meeting and was awarded the best paper by Janick Bergeron.  Heath has also co-authored or reviewed many of Cliff’s papers.  Heath has been a member of IEEE & Accellera Verilog and SystemVerilog committees.  Heath holds a BSCS from New Mexico Tech.


Register now and bring your colleagues!

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