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DVClub Austin – December 11, 2019 – Ashutosh Moghe, Ken Matthews & Xiushan Feng

Details
Date:

December 11, 2019

Time:

11:30 am - 01:30 pm

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Organizer

DVClub

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Venue

Norris Conference Center

2525 W Anderson Ln #365, Austin, TX 78757

Austin, TX, US, 78757

Please join us on December 11, 2019 at the Norris Conference Center for a catered lunch and networking.  Ashutosh Moghe, a verification engineer at Qualcomm, Ken Matthews, a verification engineer at Samsung, and Xiushan Feng, formal verification group leader at Samsung, will be our guest speakers.



  • 11:30am — Doors Open / Networking

  • 12:00pm — Lunch / Presentations by Ashutosh Moghe, Ken Matthews, & Xiushan Feng

  • 1:00pm   — Networking


 Presentation #1


 “Verification of a Modern Branch Predictor” by Ken Matthews (Samsung) & Ashutosh Moghe (Qualcomm)


A branch predictor lies at the heart of the front-end design for any modern processor, but they are notoriously hard to verify. This daunting task involves both functional and performance verification. Stimulus can be tricky as a combination of small and big program traces are required to ascertain how fast the branch training is happening and its accuracy. More importantly, where does this stimulus come from?


 In this presentation, Ashu and Ken will describe how they and their team from the Samsung Austin R&D center used a SystemVerilog constrained-random approach to tackle this challenging problem. Their method was able to create traces containing branches which have positional displacement with respect to density or sparsity, along with complicated branch patterns with deep nesting. This SystemVerilog based approach also provides several controls to generate effective traces which stresses the prediction logic.



  • Ashutosh Moghe is currently a staff verification engineer at Qualcomm here in Austin, where he is involved with DSP core verification. Previous to that he’s worked as a design verification engineer at both Samsung and Freescale. Ashu received a degree in Electronics from the University of Mumbai, as well as a Master’s degree in Computer Engineering from the University of Southern California.



  • Ken Matthews is a senior staff engineer at Samsung’s Austin R&D Center where he has lead a verification team through 3 chip tapeouts. At Samsung he has been involved primarily with front end CPU verification, including work with branch prediction and performance modeling. Prior to Samsung he has worked in verification roles at AMD, Intrinsity, ARM, TriMedia and Motorola/Freescale. Ken received a degree in Electrical and Computer Engineering from the University of Texas at Austin.


 


Presentation #2


“Sequential Equivalence Checking Beyond Clock Gating” by Xiushan Feng (Samsung)


In the past decade, the usage of formal sequential equivalence checking has increased significantly within major semiconductor companies. Sequential equivalence checking has become the de facto tool for verifying clock gating optimizations and RTL to RTL transformation.  With broad scale adoption by designers and verification engineers, it has been proven to be one of the most powerful application of formal verification tools. In this presentation, the speaker will give an overview of the technology and provide a few key applications as examples. In addition to that, the speaker will share some advanced techniques that can achieve full proofs – highest coverage – for a few complicated sequential equivalence checking problems.   



  • Xiushan Feng is the leader of formal verification group at Samsung Austin R&D Center and San Jose Advanced Computing Lab. He received a PhD degree in formal verification from University of British Columbia at Vancouver, Canada.  Before joining Samsung, he led formal verification effort at Oracle Labs, NVidia, Freescale, and AMD.  He has 6 verification patents and published more than 30 technical papers. 


 


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