Come celebrate the Christmas season with another DVClub lunch. As always, this is a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible.

This time around we are pleased to hear from John Dickol from over at Samsung who will be presenting "I Didn't Know Constraints Could Do That!" Come learn how to teach your old constraints new tricks. We're also pleased to have a tutorial by Heath Chambers of HMC Design Verification & Sunburst Design. Heath is a professional trainer who will be offering up some world-class training to us for absolutely free. Heath will be presenting "SystemVerilog and UVM Virtual Interfaces for Class-Based Testing."

This will be another awesome event, we look forward to seeing you there!

Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, Dec. 6, 2017 from 11:30 AM to 1:30 PM (CST)
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Agenda

11:30am Doors Open / Networking
12:00pm

Lunch and Feature Presentation:

John Dickol - "I Didn't Know Constraints Could Do That!"

1:45pm

Networking

 1:00pm

Tutorial:

Heath Chambers - "SystemVerilog and UVM Virtual Interfaces for Class-Based Testing"

Registration Now Open - Click to RSVP

Keynote Presentation:

"I Didn't Know Constraints Could Do That!" by John Dickol, Samsung Austin Research & Design Center

Recent advances in SystemVerilog constraint solver performance make it practical to use more complex constraints in verification environments.  This presentation will review some lesser-known SystemVerilog constraint features (soft constraints, hierarchical constraints, array reduction constraints) and provide working examples of using these and other features to create constrained stimulus for complex real-world CPU/SOC verification problems such as testbench configuration, memory map allocation, etc.

About John Dickol:

John Dickol is a Principal Engineer at the Samsung Austin Research and Design Center (SARC) where he is currently developing verification tools and methodologies and looking for new ways to apply SystemVerilog constraints.  Before joining SARC, he led verification teams for SOC and DSP projects at MediaTek, Analog Devices, Intel, and IBM.  John has a BSEE from Lehigh University and a MSEE from Syracuse University.  He has 5 U.S. patents.

Tutorial:

"SystemVerilog and UVM Virtual Interfaces for Class-Based Testing" by Heath Chambers, HMC Design Verification, Inc. & Sunburst Design

Virtual interfaces are a common structure to tie a class-based testbench to a Design Under Test (DUT). This tutorial will describe the progression of virtual interface usage from simple virtual interface handle passing, to an OVM-like common storage object database to a UVM configuration database, how each works, and their advantages and disadvantages.

About Heath Chambers:

Heath Chambers is President of HMC Design Verification, Inc., a company that specializes in design and verification consulting and high tech training.  Heath has 20 years of ASIC and system verification experience, including 17 years teaching Verilog, SystemVerilog, UVM and synthesis with Cliff Cummings of Sunburst Design, and three years Specman Basic Training for Verisity.  Heath presented "How to Verify a Switch" at the first annual Verisity User's Group meeting and was awarded the best paper by Janick Bergeron.  Heath has also co-authored or reviewed many of Cliff's papers.  Heath has been a member of IEEE & Accellera Verilog and SystemVerilog committees.  Heath holds a BSCS from New Mexico Tech.