Spring break is approaching, but who has time for the beach? You'd rather be spending time with us at DVClub!
As always, this is a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Come catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible.
More details to follow!
This will be another awesome event, we look forward to seeing you there.
Norris Conference Center
2525 W Anderson Ln #365
Austin, TX 78757
Wednesday, March 8, 2017 from 11:30 AM to 1:30 PM (CST)
|11:30am||Doors Open / Networking|
Lunch and Presentations
Registration Open Soon
Title: Detoxify Your Schedule With A Low-Fat UVM Environment
It has been widely accepted that a test environment must be portable from unit-level to higher levels of integration. Reasons cited for this range from higher verification quality to increased verification efficiency. However, the development cost in making things portable is often taken for granted, and the decision to port is often done without an honest cost/benefit analysis. Porting a unit environment to a higher level is not always the most practical way to find new bugs, increase coverage, or otherwise improve the overall quality of verification.
This presentation proposes the use of self-checking stimulus using UVM sequences as an alternative checking methodology to traditional UVM scoreboarding. The methodology proposed can significantly reduce the development time spent on building and maintaining verification infrastructure. The presentation also discusses the benefits and risks of self-checking stimulus and how to address the risks, including non-portability of the results checkers from unit to full-chip.
Nihar Shah has spent 16 years in design verification, especially coding and architecting testbenches using UVM and SystemVerilog. In the past he has worked at Intel and Marvell on application processors for cell phones. Most recently he was part of the Project RAPID team at Oracle Labs, and has just started a new position at ARM. Given the rising complexity of designs, he is determined to find more efficient ways of achieving high-quality verification in shorter times.
Multi-Processor Memory Scoreboard: A multi-processor memory ordering and data consistency checker
In this presentation a verification architecture called Multi-Processor Memory Scoreboard (also referred as MPMS, the checker, the scoreboard) developed at Samsung Austin Research & Development Center is described. This is a RTL simulation based scoreboard which performs data consistency and memory ordering checks as required by ARMv8 ISA memory model and finds RTL errors very close to the failure point. Along with the knowledge of architectural memory ordering requirements, the scoreboard employs age-order and time-order relations of instructions of the test programs and performs data consistency and memory ordering checks.
Have 11+ years of CPU verification experience. Currently working in SARC (Samsung Austin R&D Center) since Oct 2012 on CPU verification. Before that I was working in Nvidia on CPU verification as well. Most of my verification experience is focused on memory ordering and consistency, coherency and MP verification with leading stimulus, checker and testbench developments.
Detoxify Your Schedule With A Low-Fat UVM Environment