DVClub comes to Fort Collins!
Join us on Thursday, February 23 for a very special occassion, the first ever Fort Collins DVClub event.
We're kicking things off in style with two presentations. First up is industry stalwart Cliff Cummings. If you've been to any technical conference sometime recently, you might have already had the chance to listen to one of Cliff's presentations. Always both entertaining as well as informative, Cliff has won many awards for his speaking skills. Cliff will be talking about best practices for using SystemVerilog assertions and bind files.
For our second speaker we have a local verification engineer, Jeremy Ridgeway from Broadcom. Also an experienced, award-winning speaker, Jeremy will be helping to clear up some of the deep dark mysteries around the SystemVerilog constraint solver.
As always, this is includes a free catered lunch with plenty of opportunity to learn about what's going on in the local verification community. Come catch up with old friends and colleagues, meet new friends, and network with others in the industry. Special thanks once again to our DVClub Sponsors for making this event possible.
Stick around after the lunch presentations for a tutorial from Cadence, one of our DVClub sponsors. Matt Diehl will be talking about metric-driven verification, and the Vmanager tool.
Yes we have swag! Free 10 Year Anniversary T-Shirts will be handed out ath the door to the first 30 attendees. Also, a $75 Amazon Gift Card will be raffled off at the end of the event!
We look forward to seeing you there!
Fort Collins Marriott
350 East Horsetooth Road
Fort Collins, CO 80525
Thursday, Feb. 23, 2017
|11:30am||Doors Open / Networking|
|12:00pm - 12:30pm||
Cliff Cummings presents "SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage"
|12:30pm - 1:00pm||Jeremy Ridgeway presents "The Objectification of SystemVerilog Constraints"|
|1:00pm - 1:10pm||Networking|
|1:10pm - 1:40pm||
Tutorial: Next Generation Verification Planning and Management Solution Overview (vManagerTM) (Cadence Design Systems)
Presentation by Cliff Cummings, President, Sunburst Design:
SystemVerilog Assertions - Bindfiles & Best Known Practices for Simple SVA Usage
SystemVerilog Assertions (SVA) can be added directly to the RTL code or be added indirectly through bindfiles. Best known practices suggest that it is better to add most assertions using bindfiles. This paper will explain why adding assertions directly to the RTL code can be problematic and why bindfiles solve many of the problems. This paper also explains how to use bindfiles efficiently and why engineers should generally use concurrent assertions while avoiding immediate assertions. This paper will also give assertion coding guidelines and styles that help reduce assertion coding effort, assertion coding mistakes and encourage designers to be more proactive in adding assertions to their designs.
Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world-class SystemVerilog, Synthesis and UVM Verification training. Cliff has presented hundreds of SystemVerilog seminars and training classes and has been a featured speaker at multiple world-wide SystemVerilog and Assertion Based Verification seminars. Cliff has been an active participant on every IEEE Verilog and SystemVerilog committee, and has presented more than 50 papers on Verilog & SystemVerilog related design, synthesis, and OVM/UVM verification techniques, including more than 20 that were voted "BestPaper." Cliff holds a BSEE from Brigham Young University and an MSEE from Oregon State University.
Presentation by Jeremy Ridgeway, Broadcom:
"The Objectification of SystemVerilog Constraints"
The SystemVerilog constraint solver, much like many formal tools, is built with a boolean satisfiability (SAT) modulo theory (SMT) solver. While much of SystemVerilog is imperative -- code acts like a recipe -- constrained random value generation is functional -- ordering may be abstract -- and declarative -- algorithmically static. So? As long as it just works, who cares? Well, there is no implicit declarative requirement for the SAT solver. Constraints need not be treated as if they can only be implemented once. SystemVerilog Constraints are not hardware! Instead, we present a generic constraint container class that encapsulates the constraint within simple software objects. The same test bench random value may then be constrained by wholly different constraint objects (inside range becomes inside set or distribution or constant or ... ) determined and constructed during simulation via programming interface or even specified on the command-line. We have successfully employed this approach at Broadcom in multiple projects over the past five years.
Jeremy Ridgeway has seventeen years of computer hardware verification experience, specializing in serial protocols, such as PCI-Express and SAS (Serial Attached SCSI). He has worked at LSI Logic, Sierra Logic, and Emulex before all were purchased by Avago Technologies, which of course, bought and became Broadcom. Jeremy holds a Bachelor of Science in Computer Engineering from the University of Arizona, and a Masters of Science in Electrical Engineering from the University of Alabama. Prior to joining LSI/Broadcom in 2011, Jeremy was a PhD candidate researching Boolean Satisfiability at the University of Trento, in Trento, Italy.
Matt Diehl, Applications Engineer, Cadence Design Systems
"Next Generation Verification Planning and Management Solution Overview (vManagerTM)"
Cadence vManagerTM Metric-Driven Signoff Platform, enabled by client server technology is the only second generation verification planning and management solution for pre-silicon functional verification. This enterprise class solution connects people and process’s for small to ultra-large verification projects, and from simple standalone test execution to large-scale database-enabled metric-driven verification (MDV) programs. With the vManagerTM platform, you benefit from optimal resource utilization, higher quality silicon, and a more predictable path to verification closure. The demonstration of vManagerTM will show all of the primary aspects of the tool, from creation of an executable verification plan to reporting of results. The vManagerTM process starts with a UVM or software test which is executed by a built in regression environment with a direct controllability to load sharing utilities on the farm. Tests can be driven by vMangerTM or collected from the users automation scripts. Test triage and coverage analysis is performed thru a powerful GUI based intuitive user interface, the later is unified with the industry leading IMC coverage environment from Incisive. Significant productivity is achieve by organizing the metrics against a verification plan( vPlan), effectively back annotating results to your goals. vManagerTM then supports tracking of progress over time and has built in chart creation utilities to visualize status of any metric contained in the SQL database. Charts, Regression and vPlan results can then produce clickable HTML reports which can also be displayed over the web as dashboards. Last, thru a powerful API, vManagerTM can also integrate with popular external enterprise tools, such as continuous integration tools like Jenkins, or bug tracking tools such as Bugzilla.
Matt Diehl is an Applications Engineer with Cadence Design Systems in Boise, Idaho. He has been with Cadence for 3 years. Matt's work has been focused around Verification-IP, Metric-Driven Verification methodologies, and automation. Prior to working with Cadence, Matt was a design verification and tools engineer at Intel Corporation for 6 years.